Automatic application specific floating-point unit generation

ABSTRACT

This paper describes the creation of custom floating point units (FPUs) for Application Specific Instruction Set Processors (ASIPs). ASIPs allow the customization of processors for use in embedded systems by extending the instruction set, which enhances the performance of an application or a class of applications. These extended instructions are manifested as separate hardware blocks, making the creation of any necessary floating point instructions quite unwieldy. On the other hand, using a predefined FPU includes a large monolithic hardware block with considerable number of unused instructions. A customized FPU will overcome these drawbacks, yet the manual creation of one is a time consuming, error prone process. This paper presents a methodology for automatically generating floating-point units (FPUs) that are customized for specific applications at the instruction level. Generated FPUs comply with the IEEE754 standard, which is an advantage over FP format customization. Custom FPUs were generated for several Mediabench applications. Area savings over a fully-featured FPU without resource sharing of 26%-80% without resource sharing and 33%-87% with resource sharing, were obtained. Clock period increased in some cases by up to 9.5% due to resource sharing.

REFERENCES

• 1: Jian Liang , Russell Tessier , Oskar Mencer, Floating Point Unit Generation and Evaluation for FPGAs, Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.185, April 09-11, 2003
• 2: Altaf Abdul Gaffar , Wayne Luk , Peter Y. K. Cheung , Nabeel Shirazi, Customising Floating-Point Designs, Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.315, September 22-24, 2002
• 3: Philip Brisk , Adam Kaplan , Majid Sarrafzadeh, Area-efficient instruction set synthesis for reconfigurable system-on-chip designs, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996679]
• 4: N Moreano, E Borin, C Souza, and G Araujo. Efficient Datapath Merging for Partially Reconfigurable Architectures. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 24, pages 969--980, July 2005.
• 5: Werner Geurts , Francky Catthoor , Hugo de Man, Quadratic zero-one programming based synthesis of application specific data paths, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.522-525, November 07-11, 1993, Santa Clara, California, United States
• 6: Junhyung Um , Jae-hoon Kim , Taewhan Kim, Layout-driven resource sharing in high-level synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.614-618, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774663]
• 7: Chia-Jeng Tseng and D. P. Siewiorek. Automated Synthesis of Data Paths in Digital Systems. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 5, July 1986.
• 8: Charles Y. Hitchcock, III , Donald E. Thomas, A method of automatic data path synthesis, Proceedings of the 20th conference on Design automation, p.484-489, June 27-29, 1983, Miami Beach, Florida, United States
• 9: Oliver Bringmann , Wolfgang Rosenstiel, Resource sharing in hierarchical synthesis, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.318-325, November 09-13, 1997, San Jose, California, United States
• 10: S. Raje , R. A. Bergamaschi, Generalized resource sharing, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.326-332, November 09-13, 1997, San Jose, California, United States
• 11: E. M. Witte , A. Chattopadhyay , O. Schliebusch , D. Kammler, Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation, Proceedings of the 2005 International Conference on Computer Design, p.193-199, October 02-05, 2005 [doi>10.1109/ICCD.2005.25]
• 12: K Schoofs, G Goossens, and HG Man. Bit-Alignment in Hardware Allocation for Multiplexed DSP Architectures. In Proceedings of the 4th European Conference on Design Automation with the European Event in ASIC Design, pages 289--293, Feb 1993.
• 13: Cliquer. http://users.tkk.fi/pat/cliquer.html.
• 14: SimpleScalar Tool Set. http://www.simplescalar.com.
• 15: IEEE standard for binary floating-point arithmetic, 1985.
• 16: David A. Patterson , John Hennessy, Computer Organization and Design, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2004
• 17: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 18: Synopsys Tool Set. http://www.synopsys.com.
• 19: Leon Stok, False loops through resource sharing, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.345-348, November 1992, Santa Clara, California, United States