Area optimization of multi-cycle operators in high-level synthesis

ABSTRACT

Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need several cycles to execute one operation, but the entire functional unit is not used in any cycle. Additionally, the execution of operations over wider multi-cycle operators is unfeasible if their results must be available in a smaller number of cycles than the functional unit delay. This obliges to add new functional resources to the datapath even if multi-cycle operators are idle when the execution of the operation begins.

In this paper a new design technique to overcome the restricted reusability of multi-cycle operators is presented. It reduces the area of these functional units allowing their internal reuse when executing one operation. It also expands the possibilities of common hardware sharing as it allows the partial use of multi-cycle operators to calculate narrower operations faster than the functional unit delay. This technique is applied as an optimization phase at the end of the high-level synthesis process, and can optimize the circuits synthesized by any high-level synthesis tool.

REFERENCES

• 1: N. Park, and A. Parker. "Sehwa: A Software Package for Synthesis of Pipelines from Behavioural Specifications". IEEE Trans. on CAD, March 1988.
• 2: K. S. Hwang, A. E. Casavant, C. T. Chang, and M. A. d'Abreu. "Scheduling and Hardware Sharing in Pipelined Data Paths". In Proc. ICCAD 1989.
• 3: Seda Ogrenci Memik , Ryan Kastner , Elaheh Bozorgzadeh , Majid Sarrafzadeh, A scheduling algorithm for optimization and early planning in high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.33-57, January 2005 [doi>10.1145/1044111.1044115]
• 4: Sumit Gupta , Nick Savoiu , Nikil Dutt , Rajesh Gupta , Alex Nicolau , Timothy Kam , Michael Kishinevsky , Shai Rotem, Coordinated transformations for high-level synthesis of high performance microprocessor blocks, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514140]
• 5: Apostolos A. Kountouris , Christophe Wolinski, Efficient scheduling of conditional behaviors for high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.380-412, July 2002 [doi>10.1145/567270.567272]
• 6: Jinhwan Jeon , Daehong Kim , Dongwan Shin , Kiyoung Choi, High-level synthesis under multi-cycle interconnect delay, Proceedings of the 2001 conference on Asia South Pacific design automation, p.662, January 2001, Yokohama, Japan [doi>10.1145/370155.370576]
• 7: S. Park, and K. Choi. "Performance-Driven High-Level Synthesis with Bit-Level Chaining and Clock Selection". IEEE Trans. on CAD, February 2001.
• 8: Zhan Yu , Kei-Yong Khoo , Alan N. Willson, Jr., The use of carry-save representation in joint module selection and retiming, Proceedings of the 37th conference on Design automation, p.768-773, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337773]
• 9: V. Raghunathan, S. Ravi, and G. Lakshminarayana. "Integrating Variable-Latency Components into High-Level Synthesis". IEEE Trans. on CAD, October 2000.
• 10: Jianwen Zhu , Daniel D. Gajski, Soft scheduling in high level synthesis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.219-224, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309917]
• 11: Rafael Ruiz-Sautua , María C. Molina , José M. Mendías , Rom´n Hermida, Pre-synthesis optimization of multiplications to improve circuit performance, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany