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Toward a scalable test methodology for 2D-mesh Network-on-Chips
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
SESSION: Testing NoCs table of contents
Pages: 367 - 372  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Authors
Kim Petersén  Royal Institute of Technology (KTH), Kista, Sweden
Johnny Öberg  Royal Institute of Technology (KTH), Kista, Sweden
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
: The EDA Consortium
EDAA : European Design and Automation Association
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
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Downloads (6 Weeks): 8,   Downloads (12 Months): 50,   Citation Count: 0
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ABSTRACT

This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Standard IEEE 1500. Standard Testability Method for Embedded Core-based Integrated Circuits. IEEE 2005.
 
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A. M. Amory, E. Brião, É Cota, M. Lubaszewski, F. G. Moraes. A Scalable Test Strategy for Network-on-Chip Routers. Proc. of ITC 2005.
 
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B. Vermeulen, J. Dielissen, and K. Goossens. Bringing Communication Networks on a Chip: Test and Verification Implications. IEEE Communications Magazine, vol. 41--9, 2003, pp. 74--81.
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K. Petersén, J Öberg. Utilizing NoC Switches as BIST-structures in 2D-Mesh Network-on-Chip. Future Interconnects and Network on Chip Workshop, 2006.
 
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C. Grecu, P. Pande, A. Ivanov, R. Saleh. BIST for Network-on-Chip Interconnect Infrastructures.

Collaborative Colleagues:
Kim Petersén: colleagues
Johnny Öberg: colleagues