| Toward a scalable test methodology for 2D-mesh Network-on-Chips |
| Full text |
Pdf
(232 KB)
|
| Source
|
Design, Automation, and Test in Europe
archive
Proceedings of the conference on Design, automation and test in Europe
table of contents
Nice, France
SESSION: Testing NoCs
table of contents
Pages: 367 - 372
Year of Publication: 2007
ISBN:978-3-9810801-2-4
|
|
Authors
|
|
Kim Petersén
|
Royal Institute of Technology (KTH), Kista, Sweden
|
|
Johnny Öberg
|
Royal Institute of Technology (KTH), Kista, Sweden
|
|
| Sponsors |
|
| Publisher |
EDA Consortium
San Jose, CA, USA
|
| Bibliometrics |
Downloads (6 Weeks): 8, Downloads (12 Months): 50, Citation Count: 0
|
|
|
ABSTRACT
This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
Standard IEEE 1500. Standard Testability Method for Embedded Core-based Integrated Circuits. IEEE 2005.
|
| |
3
|
A. M. Amory, E. Brião, É Cota, M. Lubaszewski, F. G. Moraes. A Scalable Test Strategy for Network-on-Chip Routers. Proc. of ITC 2005.
|
| |
4
|
B. Vermeulen, J. Dielissen, and K. Goossens. Bringing Communication Networks on a Chip: Test and Verification Implications. IEEE Communications Magazine, vol. 41--9, 2003, pp. 74--81.
|
 |
5
|
|
| |
6
|
|
| |
7
|
|
| |
8
|
|
| |
9
|
|
| |
10
|
Partha Pratim Pande , Cristian Grecu , Andre Ivanov , Resve Saleh , Giovanni De Micheli, Design, Synthesis, and Test of Networks on Chips, IEEE Design & Test, v.22 n.5, p.404-413, September 2005
[doi> 10.1109/MDT.2005.108]
|
| |
11
|
K. Petersén, J Öberg. Utilizing NoC Switches as BIST-structures in 2D-Mesh Network-on-Chip. Future Interconnects and Network on Chip Workshop, 2006.
|
| |
12
|
|
| |
13
|
|
| |
14
|
|
| |
15
|
E. Cota , M. Kreutz , C. A. Zeferino , L. Carro , M. Lubaszewski , A. Susin, The Impact of NoC Reuse on the Testing of Core-based Systems, Proceedings of the 21st IEEE VLSI Test Symposium, p.128, April 27-May 01, 2003
|
| |
16
|
C. Grecu, P. Pande, A. Ivanov, R. Saleh. BIST for Network-on-Chip Interconnect Infrastructures.
|
|