| Interactive presentation: An FPGA implementation of decision tree classification |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe
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Nice, France
SESSION: IP designs for media processing and other computational intensive kernels
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Pages: 189 - 194
Year of Publication: 2007
ISBN:978-3-9810801-2-4
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Authors
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Ramanathan Narayanan
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Northwestern University, Evanston, IL
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Daniel Honbo
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Northwestern University, Evanston, IL
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Gokhan Memik
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Northwestern University, Evanston, IL
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Alok Choudhary
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Northwestern University, Evanston, IL
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Joseph Zambreno
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Iowa State University, Ames, IA
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EDA Consortium
San Jose, CA, USA
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Downloads (6 Weeks): 6, Downloads (12 Months): 42, Citation Count: 0
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ABSTRACT
Data mining techniques are a rapidly emerging class of applications that have widespread use in several fields. One important problem in data mining is Classification, which is the task of assigning objects to one of several predefined categories. Among the several solutions developed, Decision Tree Classification (DTC) is a popular method that yields high accuracy while handling large datasets. However, DTC is a computationally intensive algorithm, and as data sizes increase, its running time can stretch to several hours. In this paper, we propose a hardware implementation of Decision Tree Classification. We identify the compute-intensive kernel (Gini Score computation) in the algorithm, and develop a highly efficient architecture, which is further optimized by reordering the computations and by using a bitmapped data structure. Our implementation on a Xilinx Virtex-II Pro FPGA platform (with 16 Gini units) provides up to 5.58x performance improvement over an equivalent software implementation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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