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Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
SESSION: Algorithms and applications of run-time reconfiguration table of contents
Pages: 147 - 152  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Authors
Yang Qu  Technical Research Centre of Finland (VTT), Finland
Juha-Pekka Soininen  Technical Research Centre of Finland (VTT), Finland
Jari Nurmi  Tampere University of Technology, Tampere, Finland
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
: The EDA Consortium
EDAA : European Design and Automation Association
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
Bibliometrics
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ABSTRACT

In this paper, an approach that uses dynamic voltage scaling (DVS) to reduce the configuration energy of runtime reconfigurable devices is proposed. The basic idea is to use configuration prefetching and parallelism to create excessive system idle time and apply DVS on the configuration process when such idle time can be utilized. A genetic algorithm is developed to solve the task scheduling and voltage assignment problem. With real applications, the results show that up to 19.3% of configuration energy can be reduced. When considering the reduction of the configuration energy, the results show that using more computation resources is more favorable when the configuration latency is relatively small, and using more configuration controllers is more favorable for relatively large latency.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Xilinx, datasheet and application notes, www.xilinx.com.
 
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T. D. Burd, et al, "A dynamic voltage scaled microprocessor system", IEEE JSSC, vol. 35, no. 11. pp. 1571--1580, 2000.
 
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Y. Lin, F. Li, and L. He, "Circuits and architectures for FPGA with configurable supply voltage", IEEE Trans. on VLSI, vol. 13, no. 9, pp. 1037--1047, 2005.
 
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Collaborative Colleagues:
Yang Qu: colleagues
Juha-Pekka Soininen: colleagues
Jari Nurmi: colleagues