| Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe
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Nice, France
SESSION: Algorithms and applications of run-time reconfiguration
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Pages: 147 - 152
Year of Publication: 2007
ISBN:978-3-9810801-2-4
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Authors
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Yang Qu
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Technical Research Centre of Finland (VTT), Finland
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Juha-Pekka Soininen
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Technical Research Centre of Finland (VTT), Finland
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Jari Nurmi
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Tampere University of Technology, Tampere, Finland
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EDA Consortium
San Jose, CA, USA
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Downloads (6 Weeks): 1, Downloads (12 Months): 19, Citation Count: 0
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ABSTRACT
In this paper, an approach that uses dynamic voltage scaling (DVS) to reduce the configuration energy of runtime reconfigurable devices is proposed. The basic idea is to use configuration prefetching and parallelism to create excessive system idle time and apply DVS on the configuration process when such idle time can be utilized. A genetic algorithm is developed to solve the task scheduling and voltage assignment problem. With real applications, the results show that up to 19.3% of configuration energy can be reduced. When considering the reduction of the configuration energy, the results show that using more computation resources is more favorable when the configuration latency is relatively small, and using more configuration controllers is more favorable for relatively large latency.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Xilinx, datasheet and application notes, www.xilinx.com.
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[doi> 10.1109/12.859540]
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Y. Lin, F. Li, and L. He, "Circuits and architectures for FPGA with configurable supply voltage", IEEE Trans. on VLSI, vol. 13, no. 9, pp. 1037--1047, 2005.
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