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Fully-adaptive routing: packet switching performance and wormhole algorithms
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Source Conference on High Performance Networking and Computing archive
Proceedings of the 1991 ACM/IEEE conference on Supercomputing table of contents
Albuquerque, New Mexico, United States
Pages: 654 - 663  
Year of Publication: 1991
ISBN:0-89791-459-7
Authors
S. A. Felperin  CRAAG IBM Argentina, ESLAI
L. Gravano  CRAAG IBM Argentina, ESLAI
G. D. Pifarré  CRAAG IBM Argentina, ESLAI
J. L. C. Sanz  IBM Almaden Research Center, CRAAG IBM Argentina
Sponsors
IEEE : Institute of Electrical and Electronics Engineers
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 20,   Citation Count: 11
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
K. Gunther, "Prevention of deadlocks in packetswitched data transport system," IEEE Transaclzons on Communications, vol. com-29, April 1981.
 
2
P. Merlin and P. Schweitzer, "Deadlock avoidance in store-and-forward networks. 1' Store-andforward deadlock," IEEE Transactions on Communications, vol. 28, March 1980.
 
3
W. Dally and C. Seitz, "Deadlock-free routing in multiprocessor interconnection network," 5206:TR:86, Computer Science Department, California Institute of Technology, 1986.
4
5
 
6
L. G. Valiant, "Optimality of a two-phase strategy for routing in interconnection networks," March 1982.
7
 
8
A. Ranade, "How to emulate shared memory," in Foundations of Computer Science, pp. 185- 194, 1985.
9
 
10
M. Fulgham, R. Cypher, and J. Sanz, "A comparison of SIMD hypercube routing strategies," RJ 7722 (71587), IBM Almaden Research Center, 1990.
 
11
T. Leighton, D. Lisinski, and B. Maggs, "Empirical evaluation of randomly-wired multistage networks," in ICCD'90, 1990.
12
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14
J. Patel, "Performance of processor-memory interconnections for multiprocessors," IEEE Transactions on Compulers, vol. c-30, pp. 771-780, October 1981.
 
15
C. Kruskal and M. Snir, "The performance of multistage interconnection networks for multiprocessors," IEEE Transactions on Computers, vol. c-32, pp. 1091-1098, December 1983.
 
16
D. Dins and J. Jump, "Analisys and simulations of buffered delta networks," IEEE Transactions on Computers, vol. c-30, pp. 273-282, April 1981.
 
17
G. Pfister and V. Norton, "'hot spot' contention and combining in multistage interconnection networks," IEEE Transactions on Computers, vol. c- 34, pp. 943-948, October 1985.
 
18
S. Felperin and J. Sanz, "Simulation Results on the Performance of Fully-Adaptive Minimal Deadlock-Free Routing for Meshes and Hypercubes," TR:91-06, IBM Argentina, CRAAG, March 1991.
 
19
L. Gravano, G. Pifarr6, and J. Sanz, "Adaptive Worm-hole' Lting in Tori and Hypercubes," TR:91-1 .8M Argentina - CRAAG, March 1991.
 
20
 
21
J. Ngai and C. Seitz, "Adaptive routing in multicomputers," in Opportunities and constraints of parallel computing (J. Sanz, ed.), Springer Verlag, New York, 1989.
 
22

CITED BY  11

Collaborative Colleagues:
S. A. Felperin: colleagues
L. Gravano: colleagues
G. D. Pifarré: colleagues
J. L. C. Sanz: colleagues