Delayed consistency and its effects on the miss rate of parallel programs

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Delayed consistency and its effects on the miss rate of parallel programs

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Conference on High Performance Networking and Computing archive
Proceedings of the 1991 ACM/IEEE conference on Supercomputing table of contents

Albuquerque, New Mexico, United States

Pages: 197 - 206

Year of Publication: 1991

ISBN:0-89791-459-7

Authors

Michel Dubois	Department of EE-Systems, University of Southern California, Los Angeles, CA
Jin Chin Wang	Tandem Computers Incorporated, M.P. Division, Austin, TX
Luiz A. Barroso	Department of EE-Systems, University of Southern California, Los Angeles, CA
Kangwoo Lee
Yung-Syau Chen	Department of EE-Systems, University of Southern California, Los Angeles, CA

Sponsors

IEEE : Institute of Electrical and Electronics Engineers
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 14

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Y. Afek , G. Brown , M. Merritt, A lazy cache algorithm, Proceedings of the first annual ACM symposium on Parallel algorithms and architectures, p.209-222, June 18-21, 1989, Santa Fe, New Mexico, United States [doi>10.1145/72935.72958]
	2	Sarita V. Adve , Mark D. Hill, Weak ordering—a new definition, Proceedings of the 17th annual international symposium on Computer Architecture, p.2-14, May 28-31, 1990, Seattle, Washington, United States
	3	G.M. Amdahl, "Validity of the single processor approach to achieving large-scale computing capabilities," Proc AFIPS, Vol. 30, pp.483-465, 1967.
	4	J. K. Bennett , J. B. Carter , W. Zwaenepoel, Munin: distributed shared memory based on type-specific memory coherence, ACM SIGPLAN Notices, v.25 n.3, p.168-176, Mar. 1990
	5	P. Bitar , A. M. Despain, Multiprocessor cache synchronization: issues, innovations, evolution, Proceedings of the 13th annual international symposium on Computer architecture, p.424-433, June 02-05, 1986, Tokyo, Japan
	6	B.M. Bean et al., "Bias Filter Memory for Filtering Out Unnecessary Interrogations of Cache Directories in a Multiprocessor System," U.S. Patent 4,142,234, Feb 1979.
	7	L. Borrmann and M. Herdieckerhoff, "A Coherency Model for Virtual Shared Memory," Proc. of Int. Conf. on Parallel Processing, Vol.2, pp.252-257, june 1990.
	8	L.M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Trans. on Computers, Vol. C-27, No. 12, pp. 1112-1118, Dec. 1978.
	9	M. Dubois, F.A. Briggs, I. Patil, and M. Balal~shnan, "Trace-driven Simulations of Parallel and Distributed Algorithms in Multiprocessors," Proc. int. Conf. on Parallel Processing, pp.909-916, Aug. 1976.
	10	N. Deo, C.Y. Pang, and R.E. Lord, "Two Parallel Algorithms for Shortest Path Problems," Proc. of the int. Conf. on Parallel Proc., pp. 244-253, Aug. 1980.
	11	Michel Dubois , Christoph Scheurich, Memory Access Dependencies in Shared-Memory Multiprocessors, IEEE Transactions on Software Engineering, v.16 n.6, p.660-673, June 1990 [doi>10.1109/32.55094]
	12	David V. James , Anthony T. Laundrie , Stein Gjessing , Gurindar Sohi, Scalable coherent interface, Computer, v.23 n.6, p.74-77, June 1990 [doi>10.1109/2.55503]
	13	David Kroft, Lockup-free instruction fetch/prefetch cache organization, Proceedings of the 8th annual symposium on Computer Architecture, p.81-87, May 12-14, 1981, Minneapolis, Minnesota, United States
	14	L. Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs," IEEE Transactions on Computers, Vol. C-28, No.9, pp.690-691, Sept. 1979.
	15	Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Anoop Gupta , John Hennessy, The directory-based cache coherence protocol for the DASH multiprocessor, Proceedings of the 17th annual international symposium on Computer Architecture, p.148-159, May 28-31, 1990, Seattle, Washington, United States
	16	R. L. Lee , P. C. Yew , D. H. Lawrie, Multiprocessor cache design considerations, Proceedings of the 14th annual international symposium on Computer architecture, p.253-262, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30379]
	17	Trevor N. Mudge , Richard B. Brown , William P. Birmingham , Jeffrey A. Dykstra , Ayman I. Kayssi , Ronald J. Lomax , Oyekunle A. Olukotun , Karem A. Sakallah , Raymond A. Milano, The Design of a Microsupercomputer, Computer, v.24 n.1, p.57-64, January 1991
	18	Todd Mowry , Anoop Gupta, Tolerating latency through software-controlled prefetching in shared-memory multiprocessors, Journal of Parallel and Distributed Computing, v.12 n.2, p.87-106, June 1991 [doi>10.1016/0743-7315(91)90014-Z]
	19	Mark S. Papamarcos , Janak H. Patel, A low-overhead coherence solution for multiprocessors with private cache memories, Proceedings of the 11th annual international symposium on Computer architecture, p.348-354, January 1984
	20	C. E. Scheurich, Access ordering and coherence in shared memory multiprocessors, University of Southern California, Los Angeles, CA, 1989
	21	C. Scheurich , M. Dubois, Lockup-free caches in high-performance multiprocessors, Journal of Parallel and Distributed Computing, v.11 n.1, p.25-36, Jan. 1991 [doi>10.1016/0743-7315(91)90068-K]
	22	R. Sedgewick, "Quicksort", New York: Garland Publishing, Inc., 1980.
	23	Gurindar S. Sohi , Manoj Franklin, High-bandwidth data memory systems for superscalar processors, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.53-62, April 08-11, 1991, Santa Clara, California, United States
	24	Per Stenström, A Survey of Cache Coherence Schemes for Multiprocessors, Computer, v.23 n.6, p.12-24, June 1990 [doi>10.1109/2.55497]
	25	Texas Instruments MOS Memory Data Book, pp. 7-135 to 7-147, 1989.
	26	J. Torrellas, M.S. Lam, and J.L. Hennessy, "Shared Data Placement Optimizations to Reduce Multiprocessor Cache Misses," Proc. of the 1990 Int. Conf. on Parallel Proc., Aug 1990, pp. 266-270.
	27	Charles P. Thacker , Lawrence C. Stewart , Edwin H. Satterthwaite, Jr., Firefly: A Multiprocessor Workstation, IEEE Transactions on Computers, v.37 n.8, p.909-920, August 1988 [doi>10.1109/12.2243]
	28	D. Young, "Iterative Solution of Large Linear Systems", Academic Press: New York, 1971.

CITED BY 14

	Leonidas I. Kontothanassis , Michael L. Scott , Ricardo Bianchini, Lazy release consistency for hardware-coherent multiprocessors, Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM), p.61-es, December 04-08, 1995, San Diego, California, United States
	Kourosh Gharachorloo , Madhu Sharma , Simon Steely , Stephen Van Doren, Architecture and design of AlphaServer GS320, ACM SIGPLAN Notices, v.35 n.11, p.13-24, Nov. 2000
	Roberto Giorgi , Cosimo Antonio Prete, PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.10 n.7, p.742-763, July 1999
	Fong Pong , Michel Dubois, Formal verification of complex coherence protocols using symbolic state models, Journal of the ACM (JACM), v.45 n.4, p.557-587, July 1998
	Yuanyuan Zhou , Liviu Iftode , Jaswinder Pal Sing , Kai Li , Brian R. Toonen , Ioannis Schoinas , Mark D. Hill , David A. Wood, Relaxed consistency and coherence granularity in DSM systems: a performance evaluation, ACM SIGPLAN Notices, v.32 n.7, p.193-205, July 1997
	Kourosh Gharachorloo , Madhu Sharma , Simon Steely , Stephen Van Doren, Architecture and design of AlphaServer GS320, ACM SIGARCH Computer Architecture News, v.28 n.5, p.13-24, Dec. 2000
	Fong Pong , Michel Dubois, Verification techniques for cache coherence protocols, ACM Computing Surveys (CSUR), v.29 n.1, p.82-126, March 1997
	Fong Pong , Michel Dubois, Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models, IEEE Transactions on Parallel and Distributed Systems, v.11 n.9, p.989-1006, September 2000
	Michel Dubois , Jonas Skeppstedt , Livio Ricciulli , Krishnan Ramamurthy , Per Stenström, The detection and elimination of useless misses in multiprocessors, ACM SIGARCH Computer Architecture News, v.21 n.2, p.88-97, May 1993
	Andrew Erlichson , Neal Nuckolls , Greg Chesson , John Hennessy, SoftFLASH: analyzing the performance of clustered distributed virtual shared memory, ACM SIGPLAN Notices, v.31 n.9, p.210-220, Sept. 1996
	Kuang-Chih Liu , Chung-Ta King, A Performance Study on Bounteous Transfer in Multiprocessor Sectored Caches, The Journal of Supercomputing, v.11 n.4, p.405-420, Dec. 1997
	Lance Hammond , Brian D. Carlstrom , Vicky Wong , Ben Hertzberg , Mike Chen , Christos Kozyrakis , Kunle Olukotun, Programming with transactional coherence and consistency (TCC), ACM SIGOPS Operating Systems Review, v.38 n.5, December 2004
	Weisong Shi , Weiwu Hu , Zhimin Tang, An interaction of coherence protocols and memory consistency models in DSM systems, ACM SIGOPS Operating Systems Review, v.31 n.4, p.41-54, Oct. 1997
	M. Rasit Eskicioglu, A comprehensive bibliography of distributed shared memory, ACM SIGOPS Operating Systems Review, v.30 n.1, p.71-96, Jan. 1996