A conflict-free memory design for multiprocessors

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A conflict-free memory design for multiprocessors

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Conference on High Performance Networking and Computing archive
Proceedings of the 1991 ACM/IEEE conference on Supercomputing table of contents

Albuquerque, New Mexico, United States

Pages: 46 - 55

Year of Publication: 1991

ISBN:0-89791-459-7

Authors

Honda Shing	Department of Computer Science, Michigan State University, East Lansing, MI
Lionel M. Ni	Department of Computer Science, Michigan State University, East Lansing, MI

Sponsors

IEEE : Institute of Electrical and Electronics Engineers
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	BBN Advanced Computers Inc., Cambridge, Massachusetts, Inside the TC2000 Computer, 1990.
	2	Randall D. Rettberg , William R. Crowther , Philip P. Carvey , Raymond S. Tomlinson, The Monarch Parallel Processor Hardware Design, Computer, v.23 n.4, p.18-28, 30, April 1990 [doi>10.1109/2.55467]
	3	G. F. Pfister et al., "An introduction to the IBM research parallel processor prototype (RP3)," in Experimental Parallel Computing Architectures (J. J. Dongarra, ed.), pp. 123- 140, Elsevier Science Publishers B.V., Amsterdam, 1987.
	4	D. H. Lawrie and C. R. Vora, "The prime memory system for array access," IEEE Transactions on Computers, vol. C-31, pp. 435- 442, May 1982.
	5	D. T. Harper, III , J. R. Jump, Vector access performance in parallel memories using skewed storage scheme, IEEE Transactions on Computers, v.36 n.12, p.1440-1449, Dec. 1987 [doi>10.1109/TC.1987.5009496]
	6	S. Weiss, An aperiodic storage scheme to reduce memory conflicts in vector processors, Proceedings of the 16th annual international symposium on Computer architecture, p.380-386, April 1989, Jerusalem, Israel
	7	K. Hwang , M. Dubois , D. K. Panda , S. Rao , S. Shang , A. Uresin , W. Mao , H. Nair , M. Lytwyn , F. Hsieh , J. Liu , S. Mehrotra , C. M. Cheng, OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses, Proceedings of the 4th international conference on Supercomputing, p.7-22, June 11-15, 1990, Amsterdam, The Netherlands
	8	A. J. Smith, Line (block) size choice for CPU cache memories, IEEE Transactions on Computers, v.36 n.9, p.1063-1076, Sept. 1987 [doi>10.1109/TC.1987.5009537]
	9	D. H. Lawrie, "Access and alignment of data in an array processor," IEEE Transactions on Computers, vol. C-24, pp. 1145- 1155, Dec. 1975.
	10	M. Dubois , C. Scheurich , F. Briggs, Memory access buffering in multiprocessors, Proceedings of the 13th annual international symposium on Computer architecture, p.434-442, June 02-05, 1986, Tokyo, Japan
	11	Honda Shing , Lionel M. Ni, Resource binding—a universal approach to parallel programming, Proceedings of the 1990 conference on Supercomputing, p.574-583, October 1990, New York, New York, United States

CITED BY 2

	Montse Peiron , Mateo Valero , Eduard Ayguadé , Tomás Lang, Vector multiprocessors with arbitrated memory access, ACM SIGARCH Computer Architecture News, v.23 n.2, p.243-252, May 1995
	Chunming Qiao , Rami Melhem, Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems, IEEE Transactions on Parallel and Distributed Systems, v.8 n.2, p.97-108, February 1997