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Programming costs of explicit memory localization on a large scale shared memory multiprocessor
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Source Conference on High Performance Networking and Computing archive
Proceedings of the 1991 ACM/IEEE conference on Supercomputing table of contents
Albuquerque, New Mexico, United States
Pages: 36 - 45  
Year of Publication: 1991
ISBN:0-89791-459-7
Authors
Silvio Picano  School of Electrical Engineering, Purdue University, West Lafayette, IN
Eugene D. Brooks, III  Massively Parallel Computing Initiative, Lawrence Livermore National Laboratory, Livermore, CA
Joseph E. Hoag  Massively Parallel Computing Initiative, Lawrence Livermore National Laboratory, Livermore, CA
Sponsors
IEEE : Institute of Electrical and Electronics Engineers
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
BBN Advanced Computers Inc., Inside The TC2000, Cambridge, MA 1989.
 
2
J.P. Hayes, T.N. Mudge, Q.F. Stout, S. Colley, J. Palmer, Architecture of a Hypercube Supercompurer, Proc. of the 1986 International Conf. on Parallel Processing, pp. 653-660.
 
3
S. Picano, T.L. Casavant, An Experimental Analysis of Image Correlation on Shared vs. Non-Shared Memory MIMD Parallel Computers, Proc. of the 1990 International Conf. on Parallel Processing, pp. 92-96.
 
4
L.M. Censier, P. Feautrier, A New Solution to Coherence Problems in Multicache Systems, IEEE Transactions on Computers, Vol. C-27, No. 12, Dec. 1978, pp. 1112-1118.
 
5
E.D. Brooks III, Joseph E. Hoag, A Scalable Coherent Cache System With Incomplete Directory Slate, Proc. of the 1990 International Conf. on Parallel Processing, pp. 553-554.
 
6
C. Warner, D.G. Meyer, Directory Based Cache Coherence Protocols for Shared Memory Multiprocessors, Purdue University Tech. Rep. TR-EE 90-33, West Lafayette, IN, May 1990.
 
7
E.D. Brooks III, The Indirect K-ary N-cube for a Vector Processing Environment, Parallel Computing, Vol. 6, 1988, pp. 339-348.
 
8
 
9
MC88100 RISC Microprocessor User's Manual, 2nd edition, Prentice Hall, Englewood Cliffs, NJ, 1990.
 
10
MC88200 Cache/Memory Management Unit User's Manual, 2nd edition, Prentice Hall, Englewood Cliffs, N J, 1990.
 
11
W.C. Brantley, K.P. McAuliffe, J. Weiss, RP3 Processor-Memory Element, Proc. of the 1985 International Conf. on Parallel Processing, pp. 782- 789.
 
12
G.F. Pfister, V.A. Norton, "Hot Spot" Contention and Combining in Multistage Inlerconnection Networks, Proe. of the 1985 International Conf. on Parallel Processing, pp. 790-797.
 
13
A.Gupta, W.D. Weber, T. Mowry, Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes, Proc. of the 1990 International Conf. on Parallel Processing, pp. 312-321.
 
14
P1596 Working Group, P1596/Part IIIA- SC1 Cache Coherence Overview, Tech. Rep. Rev. 0.33, IEEE Computer Society, Nov 1989.
 
15
R.L. Lee, P.C. Yew, D.H. Lawrie, Data Prefetching in Shared Memory Multiprocessors, Proc. of the 1987 International Conf. on Parallel Processing, pp. 28-31.
 
16
 
17
E.D. Brooks III, K.H. Warren, ed., The 1991 MPCI Yearly Report: The Attack of the Killer Micros, Lawrence Livermore National Laboratory Tech. Rep. UCP~L-ID-107022, Livermore, CA, March 1991.

Collaborative Colleagues:
Silvio Picano: colleagues
Eugene D. Brooks, III: colleagues
Joseph E. Hoag: colleagues