Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium® architecture

ABSTRACT

Recently SPEC1 released the next generation of its CPU benchmark, widely used by compiler writers and architects for measuring processor performance. This calls for characterization of the applications in SPEC CPU2006 to guide the design of future microprocessors. In addition, it necessitates assessing the change in the characteristics of the applications from one suite to another. Although similar studies using the retired SPEC CPU benchmark suites have been done in the past, to the best of our knowledge, a thorough characterization of CPU2006 and its comparison with CPU2000 has not been done so far. In this paper, we present the above; specifically, we analyze IPC (instructions per cycle), L1, L2 data cache misses and branch prediction, especially in CPU2006.

REFERENCES

• 1: SPEC CPU Benchmarks. http://www.spec.org/benchmarks.html.
• 2: Cameron McNairy , Rohit Bhatia, Montecito: A Dual-Core, Dual-Thread Itanium Processor, IEEE Micro, v.25 n.2, p.10-20, March 2005 [doi>10.1109/MM.2005.34]
• 3: Caliper. http://ieeexplore.ieee.org/iel5/4434/19364/00895108.pdf.
• 4: Standard Template Library Programmer's Guide. http://www.sgi.com/tech/stl/.
• 5: John L. Henning, SPEC CPU2000: Measuring CPU Performance in the New Millennium, Computer, v.33 n.7, p.28-35, July 2000 [doi>10.1109/2.869367]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Measurement techniques

General Terms:
Management, Measurement

Keywords:
SPEC CPU benchmarks, branch prediction, caches, performance evaluation