Automatic generation of embedded communication SW for heterogeneous MPSoC platforms

ABSTRACT

This paper addresses the problem of long design cycle of MPSoCs communication SW with automatic synthesis. The tool we propose takes as input a transaction level model (TLM) of MPSoC communication and outputs pin and cycle-accurate (PCA) bus drivers that can be linked to the synthesizable PCA model (PCAM).

The TL communication is simple since TLM channels abstract away protocol details. PCAM communication, in turn, includes explicit definitions for each signal and pin. However, in most cases the TLMs are not suitable for implementation since they do not reflect the MPSoC platform. Usually the designers simulate (fast) TLMs, then manually implement PCA communication.

Our communication SW synthesis transforms TL send and receive functions into platform specific PCAM bus drivers which can be automatically downloaded to the FPGA board. The presented results demonstrate the significant productivity gain achieved with our tool, with no great cost to either code size or system performance.

REFERENCES

• 1: OSCI. http://www.systemc.org/.
• 2: Thorsten Grotker, System Design with SystemC, Kluwer Academic Publishers, Norwell, MA, 2002
• 3: Daniel D. Gajski, Jianwen Zhu, Rainer Dömer, Andreas Gerstlauer, and Shuqing Zhao, SpecC: Specification Language and Design Methodology. Kluwer Academic Publishers, 2000.
• 4: Daniel D. Gajski , Rainer Domer , Junyu Peng , Andreas Gerstlauer, System Design: A Practical Guide with Specc, Kluwer Academic Publishers, Norwell, MA, 2001
• 5: Accellera. SystemVerilog 3.0, In http://www.accellera.org.

INDEX TERMS

Primary Classification:
  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.2 Design Tools and Techniques
          Subjects: Computer-aided software engineering (CASE)

General Terms:
Algorithms, Design

Keywords:
MPSoC, automatic synthesis, custom communication SW, on-chip communication, pin/cycle accurate models, platform based design, system level design, transaction level models