| On the complexity of spill everywhere under SSA form |
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Language, Compiler and Tool Support for Embedded Systems
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Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
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San Diego, California, USA
SESSION: Register and memory management
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Pages: 103 - 112
Year of Publication: 2007
ISBN:978-1-59593-632-5
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Authors
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Florent Bouchez
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LIP: CNRS -- ENS Lyon -- UCB Lyon -- INRIA, Lyon, France
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Alain Darte
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LIP: CNRS -- ENS Lyon -- UCB Lyon -- INRIA, Lyon, France
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Fabrice Rastello
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LIP: CNRS -- ENS Lyon -- UCB Lyon -- INRIA, Lyon, France
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Downloads (6 Weeks): 6, Downloads (12 Months): 57, Citation Count: 1
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ABSTRACT
Compilation for embedded processors can be either aggressive (time consuming cross-compilation) or just in time (embedded and usually dynamic). The heuristics used in dynamic compilation are highly constrained by limited resources, time and memory in particular. Recent results on the SSA form open promising directions for the design of new register allocation heuristics for embedded systems and especially for embedded compilation. In particular, heuristics based on tree scan with two separated phases -- one for spilling, then one for coloring/coalescing -- seem good candidates for designing memory-friendly, fast, and competitive register allocators. Still, also because of the side effect on power consumption, the minimization of loads and stores overhead (spilling problem) is an important issue. This paper provides an exhaustive study of the complexity of the "spill everywhere" problem in the context of the SSA form. Unfortunately, conversely to our initial hopes, many of the questions we raised lead to NP-completeness results. We identify some polynomial cases but that are impractical in JIT context. Nevertheless, they can give hints to simplify formulations for the design of aggressive allocators.
REFERENCES
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