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Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose
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Language, Compiler and Tool Support for Embedded Systems archive
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems table of contents
San Diego, California, USA
SESSION: Source-level analysis table of contents
Pages: 73 - 82  
Year of Publication: 2007
ISBN:978-1-59593-632-5
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Authors
Christophe Alias  LIP: CNRS - ENS Lyon - UCB Lyon - INRIA, Lyon, France
Fabrice Baray  LIP: CNRS - ENS Lyon - UCB Lyon - INRIA, Lyon, France
Alain Darte  LIP: CNRS - ENS Lyon - UCB Lyon - INRIA, Lyon, France
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGARCH: ACM Special Interest Group on Computer Architecture
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGPLAN: ACM Special Interest Group on Programming Languages
SIGDA: ACM Special Interest Group on Design Automation
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ACM  New York, NY, USA
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ABSTRACT

We build on prior work on intra-array memory reuse, for which a general theoretical framework was proposed based on lattice theory. Intra-array memory reuse is a way of reducing the size of a temporary array by folding, thanks to affine mappings and modulo operations, reusing memory locations when they contain a value not used later. We describe the algorithms needed to implement such a strategy. Our implementation has two parts. The first part, Bee, uses the source-to-source transformer ROSE to extract from the program all necessary information on the lifetime of array elements and to generate the code after memory reduction. The second part, Cl@k, is a stand-alone mathematical tool dedicated to optimizations on polyhedra, in particular the computation of successive minima and the computation of good admissible lattices, which are the basis for lattice-based memory reuse. Both tools are developed in C++ and use linear programming and polyhedra manipulations. They can be used either for embedded program optimizations, e.g., to limit memory expansion introduced for parallelization, or in high-level synthesis, e.g., to design memories between communicating hardware accelerators.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Christophe Alias: colleagues
Fabrice Baray: colleagues
Alain Darte: colleagues