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Enforcing isolation and ordering in STM
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Conference on Programming Language Design and Implementation archive
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation table of contents
San Diego, California, USA
SESSION: Compiled correctly table of contents
Pages: 78 - 88  
Year of Publication: 2007
ISBN:978-1-59593-633-2
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Authors
Tatiana Shpeisman  Intel Corporation, Santa Clara, CA
Vijay Menon  Intel Corporation, Santa Clara, CA
Ali-Reza Adl-Tabatabai  Intel Corporation, Santa Clara, CA
Steven Balensiefer  University of Washington, Seattle, WA
Dan Grossman  University of Washington, Seattle, WA
Richard L. Hudson  Intel Corporation, Santa Clara, CA
Katherine F. Moore  University of Washington, Seattle, WA
Bratin Saha  Intel Corporation, Santa Clara, CA
Sponsors
SIGPLAN: ACM Special Interest Group on Programming Languages
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 17,   Downloads (12 Months): 208,   Citation Count: 30
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ABSTRACT

Transactional memory provides a new concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. High-performance software transactional memory (STM) implementations thus far provide weak atomicity: Accessing shared data both inside and outside a transaction can result in unexpected, implementation-dependent behavior. To guarantee isolation and consistent ordering in such a system, programmers are expected to enclose all shared-memory accesses inside transactions.

A system that provides strong atomicity guarantees isolation even in the presence of threads that access shared data outside transactions. A strongly-atomic system also orders transactions with conflicting non-transactional memory operations in a consistent manner.

In this paper, we discuss some surprising pitfalls of weak atomicity, and we present an STM system that avoids these problems via strong atomicity. We demonstrate how to implement non-transactional data accesses via efficient read and write barriers, and we present compiler optimizations that further reduce the overheads of these barriers. We introduce a dynamic escape analysis that differentiates private and public data at runtime to make barriers cheaper and a static not-accessed-in-transaction analysis that removes many barriers completely. Our results on a set of Java programs show that strong atomicity can be implemented efficiently in a high-performance STM system.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY  30

Collaborative Colleagues:
Tatiana Shpeisman: colleagues
Vijay Menon: colleagues
Ali-Reza Adl-Tabatabai: colleagues
Steven Balensiefer: colleagues
Dan Grossman: colleagues
Richard L. Hudson: colleagues
Katherine F. Moore: colleagues
Bratin Saha: colleagues