ACM Home Page
Please provide us with feedback. Feedback
A study of thread migration in temperature-constrained multicores
Full text PdfPdf (423 KB)
Source
ACM Transactions on Architecture and Code Optimization (TACO) archive
Volume 4 ,  Issue 2  (June 2007) table of contents
Article No. 9  
Year of Publication: 2007
ISSN:1544-3566
Authors
Pierre Michaud  IRISA/INRIA, Rennes Cedex, France
André Seznec  IRISA/INRIA, Rennes Cedex, France
Damien Fetis  IRISA/INRIA, Rennes Cedex, France
Yiannakis Sazeides  University of Cyprus, Nicosia, Cyprus
Theofanis Constantinou  University of Cyprus, Nicosia, Cyprus
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 32,   Downloads (12 Months): 207,   Citation Count: 2
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1250727.1250729
What is a DOI?

ABSTRACT

Temperature has become an important constraint in high-performance processors, especially multicores. Thread migration will be essential to exploit the full potential of future thermally constrained multicores. We propose and study a thread migration method that maximizes performance under a temperature constraint, while minimizing the number of migrations and ensuring fairness between threads. We show that thread migration brings important performance gains and that it is most effective during the first tens of seconds following a decrease of the number of running threads.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
ATMI. http://www.irisa.fr/caps/projects/ATMI/.
2
3
 
4
5
 
6
Gunther, S., Binns, F., Carmean, D., and Hall, J. 2001. Managing the impact of increasing microprocessor power consumption. Intel Technology Journal 5, 1 (Feb.).
 
7
8
 
9
Intel. 2004. Intel Pentium 4 processor on 90nm process thermal and mechanical design guidelines. Document 300564.
 
10
ITRS. 2004. International technology roadmap for semiconductors. http://www.itrs.net.
 
11
12
 
13
 
14
15
 
16
Michaud, P. and Sazeides, Y. 2006. Scheduling issues on thermally constrained processors. Tech. Rep. PI-1822, IRISA. Also published as INRIA report RR-6006.
 
17
Michaud, P., Sazeides, Y., Seznec, A., Constantinou, T., and Fetis, D. 2005. An analytical model of temperature in microprocessors. Tech. Rep. PI-1760, IRISA. Also published as INRIA report RR-5744.
 
18
Moore, J., Sharma, R., Shih, R., Chase, J., Patel, C., and Ranganathan, P. 2004. Going beyond CPUs: The potential for temperature-aware data centers. In Proceedings of the First Workshop on Temperature-Aware Computer Systems.
 
19
Naffziger, S., Stackhouse, B., and Grutkowski, T. 2005. The implementation of a 2-core multi-threaded Itanium-family processor. In IEEE International Solid-State Circuits Conference Digest of Technical Papers.
20
 
21
Pham, D., Behnen, E., Bolliger, M., Hofstee, H. P., Johns, C., Kahle, J., Kameyama, A., Keaty, J., Le, B., Masubuchi, Y., Posluszny, S., Riley, M., Suzuoki, M., Wang, M., Warnock, J., Weitzel, S., Wendel, D., and Yazawa, K. 2005. The design methodology and implementation of a first-generation CELL processor: A multi-core SoC. In Proceedings of the IEEE 2005 Custom Integrated Circuits Conference.
 
22
Poirier, C., McGowen, R., Bostak, C., and Naffziger, S. 2005. Power and temperature control on a 90nm Itanium-family processor. In EEE International Solid-State Circuits Conference Digest of Technical Papers.
23
 
24
Rohou, E. and Smith, M. 1999. Dynamically managing processor temperature and power. In Proceedings of the 2nd Workshop on Feedback-Directed Optimization.
 
25
Rotem, E., Naveh, A., Moffie, M., and Mendelson, A. 2004. Analysis of thermal monitor features of the Intel Pentium M processor. In First Workshop on Temperature-Aware Computer Systems.
 
26
Samson, E., Machiroutu, S., Chang, J.-Y., Santos, I., Hermerding, J., Dani, A., Prasher, R., and Song, D. 2005. Interface material selection and a thermal management technique in second-generation platforms built on Intel Centrino Mobile Technology. Intel Technology Journal 9, 1 (Feb.).
 
27
 
28
29
 
30
Srinivasan, J. and Adve, S. 2005. The importance of heat-sink modeling for DTM. In Proceedings of the 4th Annual Workshop on Duplicating, Deconstructing, and Debunking.
 
31
Tendler, J., Dodson, J., Field, J., Le, H., and Sinharoy, B. 2002. POWER4 system architecture. IBM Journal of Research and Development 46, 1 (Jan.).
 
32
Tschanz, J., Narendra, S., Ye, Y., Bloechel, B., Borkar, S., and De, V. 2003. Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE Journal of Solid-State Circuits 38, 11 (Nov.), 1838--1845.


Collaborative Colleagues:
Pierre Michaud: colleagues
André Seznec: colleagues
Damien Fetis: colleagues
Yiannakis Sazeides: colleagues
Theofanis Constantinou: colleagues