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ABSTRACT
We propose signature-accelerated transactional memory (SigTM), ahybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the read-set and write-set forpending transactions and perform conflict detection between concurrent threads. All other transactional functionality, including dataversioning, is implemented in software. Unlike previously proposed hybrid TM systems, SigTM requires no modifications to the hardware caches, which reduces hardware cost and simplifies support for nested transactions and multithreaded processor cores. SigTM is also the first hybrid TM system to provide strong isolation guarantees between transactional blocks and non-transactional accesses without additional read and write barriers in non-transactional code. Using a set of parallel programs that make frequent use of coarse-grain transactions, we show that SigTM accelerates software transactions by 30% to 280%. For certain workloads, SigTM can match the performance of a full-featured hardware TM system, while for workloads with large read-sets it can be up to two times slower. Overall, we show that SigTM combines the performance characteristics and strong isolation guarantees of hardware TM implementations with the low cost and flexibility of software TM systems.
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Arnar Birgisson , Mohan Dhawan , Úlfar Erlingsson , Vinod Ganapathy , Liviu Iftode, Enforcing authorization policies using transactional memory introspection, Proceedings of the 15th ACM conference on Computer and communications security, October 27-31, 2008, Alexandria, Virginia, USA
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Cristian Perfumo , Nehir Sönmez , Srdjan Stipic , Osman Unsal , Adrián Cristal , Tim Harris , Mateo Valero, The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment, Proceedings of the 2008 conference on Computing frontiers, May 05-07, 2008, Ischia, Italy
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Richard M. Yoo , Yang Ni , Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai , Hsien-Hsin S. Lee, Kicking the tires of software transactional memory: why the going gets tough, Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures, June 14-16, 2008, Munich, Germany
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Calin Cascaval , Colin Blundell , Maged Michael , Harold W. Cain , Peng Wu , Stefanie Chiras , Siddhartha Chatterjee, Software Transactional Memory: Why is it Only a Research Toy?, Queue, v.6 n.5, September 2008
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Calin Cascaval , Colin Blundell , Maged Michael , Harold W. Cain , Peng Wu , Stefanie Chiras , Siddhartha Chatterjee, Software transactional memory: why is it only a research toy?, Communications of the ACM, v.51 n.11, November 2008
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Seth H. Pugsley , Manu Awasthi , Niti Madan , Naveen Muralimanohar , Rajeev Balasubramonian, Scalable and reliable communication for hardware transactional memory, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, October 25-29, 2008, Toronto, Ontario, Canada
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Yang Ni , Adam Welc , Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Cownie , Robert Geva , Sergey Kozhukow , Ravi Narayanaswamy , Jeffrey Olivier , Serguei Preis , Bratin Saha , Ady Tal , Xinmin Tian, Design and implementation of transactional constructs for C/C++, ACM SIGPLAN Notices, v.43 n.10, September 2008
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Ferad Zyulkyarov , Adrian Cristal , Sanja Cvijic , Eduard Ayguade , Mateo Valero , Osman Unsal , Tim Harris, WormBench: a configurable workload for evaluating transactional memory systems, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.61-68, October 26-26, 2008, Toronto, Canada
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Fuad Tabba , Mark Moir , James R. Goodman , Andrew W. Hay , Cong Wang, NZTM: nonblocking zero-indirection transactional memory, Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures, August 11-13, 2009, Calgary, AB, Canada
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Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Robert Geva , Yang Ni , Adam Welc, Towards transactional memory semantics for C++, Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures, August 11-13, 2009, Calgary, AB, Canada
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