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Speed scaling on parallel processors
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Source ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures table of contents
San Diego, California, USA
SESSION: Latency and makespan table of contents
Pages: 289 - 298  
Year of Publication: 2007
ISBN:978-1-59593-667-7
Authors
Susanne Albers  University of Freiburg, Freiburg, Germany
Fabian Müller  University of Freiburg, Freiburg, Germany
Swen Schmelzer  University of Freiburg, Freiburg, Germany
Sponsors
ACM: Association for Computing Machinery
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper we investigate algorithmic instruments leading to low powerconsumption in computing devices. While previous work on energy-efficient algorithms has mostly focused on single processor environments, in this paper we investigate multi-processor settings. We study the basic problem of scheduling a set of jobs, each specified by a release time, a deadline and a processing volume, on variable speed processors so as to minimize the total energy consumption. We first settle the complexity of speed scaling with unit size jobs. More specifically, we devise a polynomial time algorithm for agreeable deadlines and prove NP-hardness results for arbitrary release dates and deadlines. For the latter setting we also develop a polynomial time algorithm achieving a constant factor approximation guarantee that is independent of the number of processors. Additionally, we study speed scaling of jobs with arbitrary processing requirements and, again, develop constant factor approximation algorithms. We finally transform our offline algorithms into constant competitive online strategies.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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S. Albers and H. Fujiwara. Energy-efficient algorithms for flow time minimization. Proc. 23rd Annual Symposium on Theoretical Aspects of Computer Science (STACS), Springer LNCS 3884, 621--633, 2006.
 
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N. Bansal and K. Pruhs. Speed scaling to manage temperature. Proc. 22nd Annual Symposium on Theoretical Aspects of Computer Science (STACS), Springer LNCS 3404, 460--471, 2005.
 
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J.-J. Chen, T.-W. Kuo, H.-I. Lu. Power-saving scheduling for weakly dynamic voltage scaling devices. Proc. 9th International Workshop on Algorithms and Data Structures, Springer LNCS 3608, 338--349, 2005.
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Intel pressroom. http://www.intel.com/pressroom/kits/teraflops/ or http://download.intel.com/pressroom/kits/Teraflops/Teraflops Research Chip Overview.pdf
 
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K. Pruhs, R. van Stee, P. Uthaisombut. Speed scaling of tasks with precedence constraints. Proc. 3rd International Workshop on Approximation and Online Algorithms (WAOA), Springer LNCS 3879, 307--319, 2005.
 
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K. Pruhs, P. Uthaisombut and G. Woeginger. Getting the best response for your erg. Proc. 9th Scandinavian Workshop on Algorithm Theory (SWAT), Springer LNCS 3111, 15--25, 2004.
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Collaborative Colleagues:
Susanne Albers: colleagues
Fabian Müller: colleagues
Swen Schmelzer: colleagues