Reconfigurable split data caches: a novel scheme for embedded systems

ABSTRACT

This paper shows that even very small reconfigurable data caches, when split to serve data streams exhibiting temporal and spatial localities, can improve performance of embedded applications without consuming excessive silicon real estate or power. It also shows that neither higher set-associativities nor large block sizes are necessary with reconfigurable split cache organizations. We use benchmark programs from the MiBench suite to show that our cache organization outperforms an 8k unified data cache in terms of miss rates, access times, energy consumption and silicon area. Finally we show how the saved area can be utilized for supporting techniques for improving performance of embedded systems. Our design enables the cache to be divided into multiple partitions that can be used for different processor activities other than conventional caching. In this paper we have evaluated one of those options to support "prefetching".

REFERENCES

• 1: Ann Gordon-Ross , Frank Vahid , Nikil Dutt, Automatic Tuning of Two-Level Caches to Embedded Applications, Proceedings of the conference on Design, automation and test in Europe, p.10208, February 16-20, 2004
• 2: Chi-Keung Luk , Todd C. Mowry, Compiler-based prefetching for recursive data structures, Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, p.222-233, October 01-04, 1996, Cambridge, Massachusetts, United States
• 3: Chuanjun Zhang , Frank Vahid , Walid Najjar, Energy Benefits of a Configurable Line Size Cache for Embedded Systems, Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), p.87, February 20-21, 2003
• 4: Chuanjun Zhang , Frank Vahid , Walid Najjar, A highly configurable cache architecture for embedded systems, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 5: Chuanjun Zhang , Frank Vahid, Using a Victim Buffer in an Application-Specific Memory Hierarchy, Proceedings of the conference on Design, automation and test in Europe, p.10220, February 16-20, 2004
• 6: D. Burger and T. M. Austin. "The SimpleScalar Tool Set, Version 2.0", Tech. Rep. CS-1342, University of Wisconsin-Madison, June 1997.
• 7: Edward McLellan, The Alpha AXP Architecture and 21064 Processor, IEEE Micro, v.13 n.3, p.36-47, May 1993 [doi>10.1109/40.216747]
• 8: F. J. Sanchez, A. Gonzalez, and M. Valero, "Software Management of Selective and Dual Data Caches", IEEE TCCA NEWSLETTERS, March 97, pp. 3--10.
• 9: Glenn Ammons , Thomas Ball , James R. Larus, Exploiting hardware performance counters with flow and context sensitive profiling, Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation, p.85-96, June 16-18, 1997, Las Vegas, Nevada, United States
• 10: G. Lesartre and D. Hunt. PA-8500: The continuing evolution of the PA-8000 family. Proceedings of Compcon, 1997.
• 11: H. Albonesi, "Selective Cache Ways: On-Demand Cache Resource Allocation," Journal of Instruction Level Parallelism, May 2000.
• 12: J. A. Rivers and E. S. Davidson, "Reducing Conflicts in Direct-Mapped Caches with a Temporality based Design, Proc. 1996 International Conference.
• 13: Jean-Loup Baer , Tien-Fu Chen, An effective on-chip preloading scheme to reduce data access penalty, Proceedings of the 1991 ACM/IEEE conference on Supercomputing, p.176-186, November 18-22, 1991, Albuquerque, New Mexico, United States [doi>10.1145/125826.125932]
• 14: James Montanaro , Richard T. Witek , Krishna Anne , Andrew J. Black , Elizabeth M. Cooper , Daniel W. Dobberpuhl , Paul M. Donahue , Jim Eno , Gregory W. Hoeppner , David Kruckemyer , Thomas H. Lee , Peter C. M. Lin , Liam Madden , Daniel Murray , Mark H. Pearce , Sribalan Santhanam , Kathryn J. Snyder , Ray Stephany , Stephen C. Thierauf, A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor, Digital Technical Journal, v.9 n.1, p.49-62, 1997
• 15: M. B. Kamble , K. Ghose, Energy-Efficiency of VLSI Caches: A Comparative Study, Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, p.261, January 04-07, 1997
• 16: Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
• 17: M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, p.3-14, December 02-02, 2001 [doi>10.1109/WWC.2001.15]
• 18: M. Tomasko, S. Hadjiyiannis, and W. A. Najjar, "Experimental Evaluation of Array Caches", IEEE TCCA Newslatters, March 97, pp. 11--16.
• 19: Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th annual international symposium on Computer Architecture, p.364-373, May 28-31, 1990, Seattle, Washington, United States
• 20: Osman S. Unsal , Israel Koren , C. Mani Krishna , Csaba Andras Moritz, The Minimax Cache: An Energy-Efficient Framework for Media Processors, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.131, February 02-06, 2002
• 21: Park Jung-Wook , Kim Cheong-Ghil , Lee Jung-Hoon , Kim Shin-Dug, An energy efficient cache memory architecture for embedded systems, Proceedings of the 2004 ACM symposium on Applied computing, March 14-17, 2004, Nicosia, Cyprus [doi>10.1145/967900.968079]
• 22: Parthasarathy Ranganathan , Sarita Adve , Norman P. Jouppi, Reconfigurable caches and their application to media processing, Proceedings of the 27th annual international symposium on Computer architecture, p.214-224, June 2000, Vancouver, British Columbia, Canada
• 23: S. J. E. Wilton and N. P. Jouppi, "CACTI: an enhanced cache access and cycle time model," IEEE Journal of Solid-State Circuits, Volume: 31 Issue: 5, May 1996, pp.677--688.
• 24: The MOSIS Service, http://www.mosis.org
• 25: V. Milutinovic, M. Tomasevic, B. Markovic, and M. Tremblay, "The Split Temporal/Spatial Cache: Initial Performance Analysis," SCIzzL-5, Mar. 1996.
• 26: Yiannakis Sazeides , James E. Smith, The predictability of data values, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.248-258, December 01-03, 1997, Research Triangle Park, North Carolina, United States

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
cache, embedded systems, locality, reconfigurability, split cache