Massively parallel processing on a chip

ABSTRACT

MppSoC is a SIMD architecture composed of a grid of processors andmemories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution of the famous massively parallel systems proposed at the end of the eighties. We claim that today such a machine may be integrated in a single chip. On one side, new design methodologies such as IP reuse and, on the other side, thepossible high level of integration on a chip let us envisage sucha revival. Some improvements of the system architecture are possible because of the high degree of integration: The mppSoC processing elements sharemost of their design with the control processor, the integrated network allows to exchange data between PEs, but also between thecontrol processor and the PE memories, and even to connect the external devices to the system. This paper presents the mppSoC architecture, a cycle-accurate bit-accurate SystemC simulator of this architecture, and a prototype of implementation on FPGA. A complete tool chain and the execution ofsome applications on the simulator and the FPGA implementation validate the modeling choices and show the effectiveness of this design.

REFERENCES

• 1: James D. Allen , David E. Schimmel, Issues in the Design of High Performance SIMD Architectures, IEEE Transactions on Parallel and Distributed Systems, v.7 n.8, p.818-829, August 1996 [doi>10.1109/71.532113]
• 2: ARM Corporation. NEON technology. http://www.arm.com/products/CPUs/NEON.html, 2006.
• 3: Tom Blank. The MasPar MP-1 architecture. In Proceedings of the IEEE Compcon Spring 1990, pages 20--24, San Francisco, CA, February 1990. IEEE Society Press.
• 4: Pete Claydon. picoChip: A massively parallel array processor. In Embedded Processor Forum, San Jose, CA, May 2003.
• 5: Robert L. Davis. The Illiac IV processing element. IEEE Transactions on Computers, 18(9):800--816, September 1969.
• 6: H. Du , M. Sanchez-Elez , N. Tabrizi , N. Bagherzadeh , M. L. Anido , M. Fernandez, Interactive Ray Tracing on Reconfigurable SIMD MorphoSys, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20144, March 03-07, 2003
• 7: Simon Duquennoy, Sébastien Le Beux, Philippe Marquet, Samy Meftali, and Jean-Luc Dekeyser. MpNoC design: Modeling and simulation. In 15th IP Based SoC Design Conference (IP--SoC 2006), Grenoble, France, December 2006.
• 8: W. Daniel Hillis, The connection machine, MIT Press, Cambridge, MA, 1989
• 9: R. Michael Hord. The Illiac IV the first supercomputer. Computer Science Press, 1982.
• 10: ITRS, International Technology Roadmap for Semiconductors. Design, 2005 edition. http://www.itrs.net/, 2005.
• 11: Brewster A. Kahle and W. Daniel Hillis. The Connection Machine model CM-1 architecture. IEEE Transactions on Systems, Mans, and Cybernetics, 19(4):707--713, July 1989.
• 12: Won Kim and Russ Tuck. MasPar MP-2 PE chip: A totally cool hot chip. In Proc. IEEE 1993 Hot Chips Symposium, Palo Alto, CA, March 1993.
• 13: Clyde P. Kruskal and Marc Snir. The performance of multistage interconnection networks for multiprocessors. IEEE Transactions on Computers, C-32(12):1091--1098, December 1983.
• 14: Sébastien Le Beux, Vincent Gagne, El Mostapha Aboulhamid, Philippe Marquet, and Jean-Luc Dekeyser. Hardware/software exploration for an anti-collision radar system. In The 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico, August 2006.
• 15: Ming-Hau Lee , Hartej Singh , Guangming Lu , Nader Bagherzadeh , Fadi J. Kurdahi , Eliseu M. C. Filho , Vladimir Castro Alves, Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor, Journal of VLSI Signal Processing Systems, v.24 n.2-3, p.147-164, Mar. 2000 [doi>10.1023/A:1008189221436]
• 16: miniMIPS overview. http://www.opencores.org/projects.cgi/web/minimips/.
• 17: ModelSim simulation and debug environment for design. http://www.model.com/.
• 18: John R. Nickolls. The design of the MasPar MP-1: A cost effective massively parallel computer. In Proc. of the IEEE Compcon Spring 1990, pages 25--28, San Francisco, CA, February 1990. IEEE Society Press.
• 19: picoChip. Pc101 picoarray. http://www.picochip.com/technology/picoarray.
• 20: Hartej Singh , Ming-Hau Lee , Guangming Lu , Nader Bagherzadeh , Fadi J. Kurdahi , Eliseu M. Chaves Filho, MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications, IEEE Transactions on Computers, v.49 n.5, p.465-481, May 2000 [doi>10.1109/12.859540]
• 21: The SoCLib project: An open modelling and simulation platform for system on chip design. http://soclib.lip6.fr/.
• 22: VSIA (Virtual Socket Interface Alliance). http://www.vsi.org/.
• 23: Xilinx, Inc. MicroBlaze home page.http://www.xilinx.com/microblaze.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Array and vector processors

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Modeling of computer architecture
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Single-instruction-stream, multiple-data-stream processors (SIMD); Multiple-instruction-stream, multiple-data-stream processors (MIMD)

General Terms:
Design

Keywords:
MasPar, SIMD, SoC, massively parallelism, mppSoC, system-on-a-chip