Performance/area efficiency in chip multiprocessors with micro-caches

ABSTRACT

This paper proposes the use of very small instruction caches, called micro-caches (μ-caches), consisting of tens to hundreds of bytes, at the bottom of the instruction delivery hierarchy in chip-multiprocessors (CMP). Multi-core architectures place a novel emphasis on the performance/area efficiency of processor cores, and we note that traditional instruction cache sizes reflect an emphasis on hit-rate performance rather than efficiency. In brief, ¼-caches reduce the area footprint of individual cores, thus allowing additional cores to fit within a given die area. We use commercial design tools and a commercial processor core to evaluate this tradeoff in the context of high-performance networking, where CMP architectures have had their greatest commercial impact to date. Our results suggest that the use of u-caches can yield a 25% improvement in efficiency relative to traditional hierarchies. In our evaluation, we consider a range of architectural options (cluster organization, non-blocking caches, cache parameters) and justify our conclusions while accounting for the errors inherent in die area estimates.

REFERENCES

• 1: Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th annual international symposium on Computer Architecture, p.364-373, May 28-31, 1990, Seattle, Washington, United States
• 2: John L. Hennessy , David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2003
• 3: Dhruba Chandra , Fei Guo , Seongbeom Kim , Yan Solihin, Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.340-351, February 12-16, 2005 [doi>10.1109/HPCA.2005.27]
• 4: Tilman Wolf , Mark A. Franklin, Performance Models for Network Processor Design, IEEE Transactions on Parallel and Distributed Systems, v.17 n.6, p.548-561, June 2006 [doi>10.1109/TPDS.2006.75]
• 5: T. Wolf , M. Franklin, CommBench-a telecommunications benchmark for network processors, Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, p.154-162, April 24-25, 2000
• 6: Gokhan Memik , William H. Mangione-Smith , Wendong Hu, NetBench: a benchmarking suite for network processors, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 7: http://www.tensilica.com
• 8: Xtensa LX Microprocessor -- Data Book, Tensilica, Inc.
• 9: Xtensa Instruction Set Simulator-User Guide, Tensilica, Inc.
• 10: John D. Davis , James Laudon , Kunle Olukotun, Maximizing CMP Throughput with Mediocre Cores, Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, p.51-62, September 17-21, 2005 [doi>10.1109/PACT.2005.42]
• 11: http://www.ecs.umass.edu/ece/wolf/nsl/software/cb
• 12: http://cares.icsl.ucla.edu/NetBench
• 13: http://viterbi.wustl.edu
• 14: Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 15: Bradford M. Beckmann , David A. Wood, Managing Wire Delay in Large Chip-Multiprocessor Caches, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.319-330, December 04-08, 2004, Portland, Oregon [doi>10.1109/MICRO.2004.21]
• 16: Jaehyuk Huh , Changkyu Kim , Hazim Shafi , Lixin Zhang , Doug Burger , Stephen W. Keckler, A NUCA substrate for flexible CMP cache sharing, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts [doi>10.1145/1088149.1088154]
• 17: Z. Chishti, M. D. Powell, and T. N. Vijaykumar, "Optimizing Replication, Communication, and Capacity Allocation in
• 18: Rakesh Kumar , Norman P. Jouppi , Dean M. Tullsen, Conjoined-Core Chip Multiprocessing, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.195-206, December 04-08, 2004, Portland, Oregon [doi>10.1109/MICRO.2004.12]
• 19: A. Agarwal, Performance Tradeoffs in Multithreaded Processors, IEEE Transactions on Parallel and Distributed Systems, v.3 n.5, p.525-539, September 1992 [doi>10.1109/71.159037]
• 20: M. Adiletta et al., "The Next Generation of Intel IXP Network Processors", in Intel Tech. Journal, Vol. 6, Iss 3, 2002.
• 21: Cisco Systems. Silicon Packet Processor in the CRS-1 Router. http://www.cisco.com/en/US/products/ps5763/index.html
• 22: P. Crowley, "Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches.", in Proc. of the HPCA-10 Workshop on Network Processors and Applications, pages 1--13. Madrid, Spain. February, 2004.
• 23: Joseph Torrellas , Chun Xia , Russell L. Daigle, Optimizing the Instruction Cache Performance of the Operating System, IEEE Transactions on Computers, v.47 n.12, p.1363-1381, December 1998 [doi>10.1109/12.737683]
• 24: David May , Dan Page , James Irwin , Henk L. Muller, Microcaches, Proceedings of the 6th International Conference on High Performance Computing, p.21-27, December 17-20, 1999

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Multiple-instruction-stream, multiple-data-stream processors (MIMD)

General Terms:
Design, Performance

Keywords:
cache hierarchies, chip multiprocessor, networking workload