By-passing the out-of-order execution pipeline to increase energy-efficiency

ABSTRACT

Out-of-order execution significantly increases the performanceof superscalar processors. The out-of-order execution mechanismis, however, energy-inefficient, which inhibits scaling superscalar processorsto high issue widths and large instruction windows. In this paper, we build on the observation that between 19% and 36% of the instructions are immediately ready for execution, even before entering the issue queue. Yet, these instructions proceed to the energy-consuming steps ofinstruction wake-up and select and they needlessly occupy space in theissue queue. To save energy, we propose for these instructions to by-pass the out-of-order execution core. Instead, we execute them on an energy-efficient single-issue in-order by-pass pipeline.The by-pass pipeline executes a significant fraction of all instructions,allowing performance-energy trade-offs with respect to the issue width of the out-of-order pipeline and to the issue queue size.By making these trade-offs, we show energy reductions of 53% for the issue queue, 33% for the register file and 31% in the write-back and wake-up logic. Performance remains almost unaffected.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures

Additional Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers

General Terms:
Design, Experimentation, Performance

Keywords:
energy-efficiency, instruction scheduling, instruction wake-up, out-of-order execution