CPU2006 working set size

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

CPU2006 working set size

Full text

Pdf (701 KB)

Source

ACM SIGARCH Computer Architecture News archive
Volume 35 , Issue 1 (March 2007) table of contents

SPECIAL ISSUE: SPEC CPU2006 analysis table of contents

Pages: 90 - 96

Year of Publication: 2007

ISSN:0163-5964

Author

Darryl Gove

Sun Microsystems Inc.

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 78, Citation Count: 5

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1241601.1241619 What is a DOI?

ABSTRACT

SPEC CPU2000 had a target memory footprint of 200 MB for the benchmarks [1], to enable the suite to run on machines with 256 MB of memory. Six years have elapsed since the release of that suite, and in that time memory sizes have increased significantly, so the memory requirements for the recently released CPU2006 reflect this. CPU2006 has been targeted to have a benchmark memory footprint of about 900MB, allowing the suite to run on machines with 1GB of memory.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	John L. Henning, "SPEC CPU2000 Memory Footprint", http://www.spec.org/cpu2000/analysis/memory/
	2	John L. Henning, SPEC CPU2006 memory footprint, ACM SIGARCH Computer Architecture News, v.35 n.1, March 2007 [doi>10.1145/1241601.1241618]
	3	Peter J. Denning, The working set model for program behavior, Communications of the ACM, v.11 n.5, p.323-333, May 1968 [doi>10.1145/363095.363141]
	4	Suleyman Sair, Mark Charney, "Memory behavior of the SPEC2000 benchmark suite", IBM Research Report RC 21852, 2000
	5	Jason F. Cantin , Mark D. Hill, Cache performance for selected SPEC CPU2000 benchmarks, ACM SIGARCH Computer Architecture News, v.29 n.4, September 2001 [doi>10.1145/563519.563522]
	6	Erik G. Hallnor , Steven K. Reinhardt, A Unified Compressed Memory Hierarchy, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.201-212, February 12-16, 2005 [doi>10.1109/HPCA.2005.4]
	7	Simple Performance Optimisation Tool. http://cooltools.sunsource.net/spot/
	8	Bob Cmelik , David Keppel, Shade: a fast instruction-set simulator for execution profiling, Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, p.128-137, May 16-20, 1994, Nashville, Tennessee, United States

CITED BY 5

	John L. Henning, Performance counters and development of SPEC CPU2006, ACM SIGARCH Computer Architecture News, v.35 n.1, March 2007
	John L. Henning, SPEC CPU2006 memory footprint, ACM SIGARCH Computer Architecture News, v.35 n.1, March 2007
	Gabriel H. Loh, A modular 3d processor for flexible product design and technology migration, Proceedings of the 2008 conference on Computing frontiers, May 05-07, 2008, Ischia, Italy
	Gabriel H. Loh, 3D-Stacked Memory Architectures for Multi-core Processors, ACM SIGARCH Computer Architecture News, v.36 n.3, p.453-464, June 2008
	Mitchell Hayenga , Chander Sudanthi , Mrinmoy Ghosh , Prakash Ramrakhyani , Nigel Paver, Accurate system-level performance modeling and workload characterization for mobile internet devices, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.54-60, October 26-26, 2008, Toronto, Canada