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Classifying interprocess communication in process network representation of nested-loop programs
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ACM Transactions on Embedded Computing Systems (TECS) archive
Volume 6 ,  Issue 2  (May 2007) table of contents
SPECIAL ISSUE SCOPES 2005
Article No. 13  
Year of Publication: 2007
ISSN:1539-9087
Authors
Alexandru Turjan  Leiden Institute of Advanced Computer Science (LIACS), Leiden, The Netherlands
Bart Kienhuis  Leiden Institute of Advanced Computer Science (LIACS), Leiden, The Netherlands
Ed Deprettere  Leiden Institute of Advanced Computer Science (LIACS), Leiden, The Netherlands
Publisher
ACM  New York, NY, USA
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ABSTRACT

New embedded signal-processing architectures are emerging that are composed of loosely coupled heterogeneous components like CPUs or DSPs, specialized IP cores, reconfigurable units, or memories. We believe that these architectures should be programmed using the process network model of computation. To ease the mapping of applications, we are developing the Compaan compiler that automatically derives a process network (PN) description from an application written in Matlab or C. In this paper, we investigate a particular problem in nested loop programs, which is about classifying the interprocess communication in the PN representation of the nested loop program. The global memory arrays present in the code have to be replaced by a distributed communication structure used for communicating data between the network processes. We show that four types of communication exist, each exhibiting different requirements when realizing them in hardware or software. We first present two compile time tests that are based on integer linear programming to decide the type of the communication. In the second part of this paper, we present alternative classification techniques that have polynomial complexity. However, in some cases, those techniques do not give a definitive answer and the ILP tests have to be applied. All present tests are combined in a hybrid classification scheme that correctly classifies the interprocess communication. In only 5% of the cases to classify, we have to rely on integer linear programming while, in the remaining 95%, the alternative techniques presented in this paper are able to correctly classify each case. The hybrid classification scheme has become an important part of our Compaan compiler.


REFERENCES

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1
Basten, T. and Hoogerbrugge, J. 2001. Efficient execution of process networks. In Communicating Process Architectures---2001, Proceedings. Bristol. 1--14.
2
 
3
Davis, Jr, II, J., Hylands, C., Kienhuis, B., Lee, E. A., Liu, J., Liu, X., Muliadi, L., Neuendorffer, S., Tsay, J., Vogel, B., and Xiong, Y. 2001. Heterogeneous concurrent modeling and design in java. Tech. Rep. Memorandum UCB/ERL M01/12 (Mar.), University of California, Dept EECS, Berkeley, CA 94720.
 
4
De Greef, E., Catthoor, F., and De Man, H. 1977. Memory size reduction through storage order optimization for embedded parallel multimedia applications. In Parallel Processing and Multimedia. Geneva.
5
 
6
Feautrier, P. 1988. Parametric Integer Programming. In RAIRO Recherche Op?rationnelle, 22, 3, 243--268.
 
7
Kahn, G. 1974. The semantics of a simple language for parallel programming. In Proc. of the IFIP Congress 74. North-Holland, Amsterdam.
8
 
9
 
10
 
11
 
12
 
13
PicoChip. 2000. http://www.picochip.com.
14
15
 
16
Rijpkema, E. 2002. Modeling task level parallelism in piece-wise regular programs. PhD thesis, Leiden Institute of Advanced Computer Science, Leiden Univerity, The Netherlands.
 
17
18
 
19
 
20
Stravers, P. and Hoogerbrugge, J. 2001. Homogeneous multiprocessoring and the future of silicon design paradigms. In Proceedings of the Int. Symposium on VLSI Technology, Systems, and Applications.
 
21
 
22
Turjan, A. and Kienhuis, B. 2003. Storage management in process networks using the lexicographically maximal preimage. In Proceedings of the IEEE 14th Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP'03). The Hague.
 
23
24
 
25
 
26
Xilinx. 2000. http://www.xilinx.com.
 
27
Zissulescu, C., Stefanov, T., Kienhuis, B., and Deprettere, E. 2003. LAURA: Leiden architecture research and exploration tool. In Proc. 13th Int. Conference on Field Programmable Logic and Applications (FPL'03).

Collaborative Colleagues:
Alexandru Turjan: colleagues
Bart Kienhuis: colleagues
Ed Deprettere: colleagues