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GURPR*: a new global software pipelining algorithm

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International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents

Albuquerque, New Mexico, Puerto Rico

Pages: 212 - 216

Year of Publication: 1991

ISBN:0-89791-460-0

Authors

Bogong Su	The College of Staten Island of The City University of New York and Tsinghua University, Beijing, China
Jian Wang	Dept. of Computer Science and Technology, Tsinghua University, Beijing, China

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 16

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Aik87	Aiken,A. and Nicolau,A., Perfect Pipelining: A New Lf~p Parallelization Technique, Research Report, 87-873, Dept. of Computer Science, Cornell Univ., 1987.
	Ebc87	Kemal Ebcioğlu, A compilation technique for software pipelining of loops with conditional jumps, Proceedings of the 20th annual workshop on Microprogramming, p.69-79, December 01-04, 1987, Colorado Springs, Colorado, United States [doi>10.1145/255305.255317]
	Fis81	Fisher, J. A., Trace Scheduling: A Technique for Global Microcode Compaction, iEEE Trans. on Computer, voI.C-30, no. 7, 1981.
	Gas89	Gasperoni, F., Compilation Techniques for VLIW Architectures,Technical Report 435, New York University, Mar.1989.
	Gro86	Thomas Gross , Monica S. Lam, Compilation for a high-performance systolic array, Proceedings of the 1986 SIGPLAN symposium on Compiler construction, p.27-38, June 25-27, 1986, Palo Alto, California, United States
	Jon90	Reese B. Jones , Vicki H. Allan, Software pipelining: a comparison and improvement, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.46-56, November 27-29, 1990, Orlando, Florida, United States
	Lab90	Labrousse, J. and Slavenburg G. A., CREATE-LIFE: A ModUlar Design Approach for High Performances ASiC's, cO MP CON '90.
	Lam87	Monica Sin-Ling Lam, A systolic array optimizing compiler, 1987
	Lee91	Roland L. Lee , Alex Y. Kwok , Fayé A. Briggs, The floating point performance of a superscalar SPARC processor, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.28-37, April 08-11, 1991, Santa Clara, California, United States
	Su86	B. Su , S. Ding , J. Xia, URPR—An extension of URCR for software pipelining, Proceedings of the 19th annual workshop on Microprogramming, p.94-103, October 15-17, 1986, New York, New York, United States
	Su87	Bogong Su , Shiyuan Ding , Jian Wang , Jinshi Xia, GURPR—a method for global software pipelining, Proceedings of the 20th annual workshop on Microprogramming, p.88-96, December 01-04, 1987, Colorado Springs, Colorado, United States [doi>10.1145/255305.255322]
	Su90	Bogong Su , Jian Wang , Zhizhong Tang , Wei Zhao , Yimin Wu, A software pipelining based VLIW architecture and optimizing compiler, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.17-27, November 27-29, 1990, Orlando, Florida, United States
	Su91	Su, B., and Wang, j., Loop-carried Dependence and the General URPR Software Pipelining Approach, Proc. of the 24th Annual Hawaii International Conference on System Sciences, Vol.2, Jan. 1991.
	Tou84	Roy F. Touzeau, A Fortran compiler for the FPS-164 scientific computer, Proceedings of the 1984 SIGPLAN symposium on Compiler construction, p.48-57, June 17-22, 1984, Montreal, Canada
	Wol91	Andrew Wolfe , John P. Shen, A variable instruction stream extension to the VLIW architecture, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.2-14, April 08-11, 1991, Santa Clara, California, United States

CITED BY 16

	Jian Wang , Andreas Krall , M. Anton Ertl , Christine Eisenbeis, Trace Software Pipelining: A Novel Technique for Parallelization of Loops with Branches, Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, p.359-362, August 24-26, 1994
	Nancy J. Warter-Perez , Noubar Partamian, Modulo scheduling with multiple initiation intervals, Proceedings of the 28th annual international symposium on Microarchitecture, p.111-119, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	Bogong Su , Wei Zhao , Zhizhong Tang , Stanley Habib, A VLIW architecture for optimal execution of branch-intensive loops, ACM SIGMICRO Newsletter, v.23 n.1-2, p.119-124, Dec. 1992
	Alessandro De Gloria , Paolo Faraboschi , Mauro Olivieri, A non-deterministic scheduler for a software pipelining compiler, ACM SIGMICRO Newsletter, v.23 n.1-2, p.41-44, Dec. 1992
	Stephen R. Vegdahl, A dynamic-programming technique for compacting loops, ACM SIGMICRO Newsletter, v.23 n.1-2, p.180-188, Dec. 1992
	Mark G. Stoodley , Corinna G. Lee, Software pipelining loops with conditional branches, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.262-273, December 02-04, 1996, Paris, France
	Nancy J. Warter , Grant E. Haab , Krishna Subramanian , John W. Bockhaus, Enhanced modulo scheduling for loops with conditional branches, ACM SIGMICRO Newsletter, v.23 n.1-2, p.170-179, Dec. 1992
	Michael Held , Manfred Glesner, Generating compilers for generated datapaths, Proceedings of the conference on European design automation, p.532-537, September 19-23, 1994, Grenoble, France
	Dragan Milicev , Zoran Jovanovic, A finite state machine based format model of software pipelined loops with conditions, Progress in computer research, Nova Science Publishers, Inc., Commack, NY, 2001
	Jiang Wang , Christine Eisenbeis, Decomposed Software Pipelining: A New Approach to Exploit Instruction Level Parallelism for Loop Programs, Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, p.3-14, January 20-22, 1993
	B. Ramakrishna Rau , Michael S. Schlansker , P. P. Tirumalai, Code generation schema for modulo scheduled loops, ACM SIGMICRO Newsletter, v.23 n.1-2, p.158-169, Dec. 1992
	B. Ramakrishna Rau, Iterative modulo scheduling: an algorithm for software pipelining loops, Proceedings of the 27th annual international symposium on Microarchitecture, p.63-74, November 30-December 02, 1994, San Jose, California, United States
	Josep Llosa , Mateo Valero , Eduard Ayguadé , Antonio González, Modulo Scheduling with Reduced Register Pressure, IEEE Transactions on Computers, v.47 n.6, p.625-638, June 1998
	Thomas M. Conte , Sumedh Sathaye, Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility, IEEE Transactions on Computers, v.49 n.8, p.814-825, August 2000
	Chris J. Newburn , Andrew S. Huang , John Paul Shen, Balancing Fine- and Medium-Grained Parallelism in Scheduling Loops for the XIMD Architecture, Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, p.39-52, January 20-22, 1993
	Dragan Milicev , Zoran Jovanovic, Control Flow Regeneration for Software Pipelined Loops with Conditions, International Journal of Parallel Programming, v.30 n.3, p.149-179, June 2002