Code duplication

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Code duplication: an assist for global instruction scheduling

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International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents

Albuquerque, New Mexico, Puerto Rico

Pages: 103 - 113

Year of Publication: 1991

ISBN:0-89791-460-0

Authors

David Bernstein	IBM Israel Scientific Center, The Technion City, Haifa 32000, Israel
Doron Cohen	IBM Israel Scientific Center, The Technion City, Haifa 32000, Israel
Hugo Krawczyk	Computer Science Department, Princeton University, New Jersey and IBM Israel Scientific Center, The Technion City, Haifa 32000, Israel

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 10

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	BR91	David Bernstein , Michael Rodeh, Global instruction scheduling for superscalar machines, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.241-255, June 24-28, 1991, Toronto, Ontario, Canada
	EN89	K. Ebcioğlu , Toshio Nakatani, A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture, Selected papers of the second workshop on Languages and compilers for parallel computing, p.213-229, May 1990, Urbana, Illinois, United States
	E85	John R. Ellis, Bulldog: a compiler for vliw architectures (parallel computing, reduced-instruction-set, trace scheduling, scientific), 1985
	FOW87	Jeanne Ferrante , Karl J. Ottenstein , Joe D. Warren, The program dependence graph and its use in optimization, ACM Transactions on Programming Languages and Systems (TOPLAS), v.9 n.3, p.319-349, July 1987 [doi>10.1145/24039.24041]
	F81	Fisher, J., "Trace scheduling: A technique for global microcode compaction", IEEE Trans. on Computers, C-30, No. 7 (July 1981), 478-490.
	GM86	Philip B. Gibbons , Steven S. Muchnick, Efficient instruction scheduling for a pipelined architecture, Proceedings of the 1986 SIGPLAN symposium on Compiler construction, p.11-16, June 25-27, 1986, Palo Alto, California, United States
	GT88	Andrew V. Goldberg , Robert E. Tarjan, A new approach to the maximum-flow problem, Journal of the ACM (JACM), v.35 n.4, p.921-940, Oct. 1988 [doi>10.1145/48014.61051]
	GO89	Groves, R.D., and Oehler, R., "An IBM second generation RISC processor architecture*, Proc. of the IEEE Conference on Computer Design, (October 1989), 134-137.
	HG83	John L. Hennessy , Thomas Gross, Postpass Code Optimization of Pipeline Constraints, ACM Transactions on Programming Languages and Systems (TOPLAS), v.5 n.3, p.422-448, July 1983 [doi>10.1145/2166.357217]
	JW89	N. P. Jouppi , D. W. Wall, Available instruction-level parallelism for superscalar and superpipelined machines, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.272-282, April 03-06, 1989, Boston, Massachusetts, United States
	N85	Alexandru Nicolau, Percolation Scheduling: A Parallel Compilation Technique, Cornell University, Ithaca, NY, 1985
	S89	"SPEC Newsletter", Systems Performance Evaluation Cooperative, Vol. 1, Issue 1, (Sep. 1989).
	W90	H. S. Warren, Jr., Instruction scheduling for the IBM RISC System/6000 processor, IBM Journal of Research and Development, v.34 n.1, p.85-92, Jan. 1990

CITED BY 10

	Michael D. Smith , Mark Horowitz , Monica S. Lam, Efficient superscalar performance through boosting, ACM SIGPLAN Notices, v.27 n.9, p.248-259, Sept. 1992
	Mark Smotherman , Shuchi Chawla , Stan Cox , Brian Malloy, Instruction scheduling for the Motorola 88110, Proceedings of the 26th annual international symposium on Microarchitecture, p.257-262, December 01-03, 1993, Austin, Texas, United States
	Nicolas Gloy , Michael D. Smith , Cliff Young, Performance issues in correlated branch prediction schemes, Proceedings of the 28th annual international symposium on Microarchitecture, p.3-14, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	Jan Hoogerbrugge , Henk Corporaal, Register file port requirements of transport triggered architectures, Proceedings of the 27th annual international symposium on Microarchitecture, p.191-195, November 30-December 02, 1994, San Jose, California, United States
	Cliff Young , Michael D. Smith, Improving the accuracy of static branch prediction using branch correlation, ACM SIGPLAN Notices, v.29 n.11, p.232-241, Nov. 1994
	Jay Bharadwaj , William Y. Chen , Weihaw Chuang , Gerolf Hoflehner , Kishore Menezes , Kalyan Muthukumar , Jim Pierce, The Intel IA-64 Compiler Code Generator, IEEE Micro, v.20 n.5, p.44-53, September 2000
	Stefan M. Freudenberger , Thomas R. Gross , P. Geoffrey Lowney, Avoidance and suppression of compensation code in a trace scheduling compiler, ACM Transactions on Programming Languages and Systems (TOPLAS), v.16 n.4, p.1156-1214, July 1994
	Gert Goossens , Johan Van Praet , Dirk Lanneer , Werner Geurts , Augusli Kifli , Clifford Liem , Pierre G. Paulin, Embedded software in real-time signal processing systems: design technologies, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Jay Bharadwaj , Kishore Menezes , Chris McKinsey, Wavefront scheduling: path based data representation and scheduling of subgraphs, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.262-271, November 16-18, 1999, Haifa, Israel
	T. Nakatani , K. Ebcioglu, Making Compaction-Based Parallelization Affordable, IEEE Transactions on Parallel and Distributed Systems, v.4 n.9, p.1014-1029, September 1993