Software pipelining

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Software pipelining: an evaluation of enhanced pipelining

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International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents

Albuquerque, New Mexico, Puerto Rico

Pages: 82 - 92

Year of Publication: 1991

ISBN:0-89791-460-0

Authors

Reese B. Jones	Department of Computer Science at Utah State University, Logan, Utah
Vicki H. Allan	Department of Computer Science at Utah State University, Logan, Utah

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 10, Citation Count: 10

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Aik88	Alexander Scott Aiken, Compaction-based parallelization, 1988
	AN88a	A. Aiken , A. Nicolau, Optimal loop parallelization, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.308-317, June 20-24, 1988, Atlanta, Georgia, United States
	AN88b	A. Aiken , A. Nicolau, A Development Environment for Horizontal Microcode, IEEE Transactions on Software Engineering, v.14 n.5, p.584-594, May 1988 [doi>10.1109/32.6136]
	AN90	A. Aiken and A. Nicolau. A realistic resourceconstrained software pipelining algorithm. Technical Report RJ 7743, IBM Research Division, San Jose, California, October 1990.
	BSKT79	U. Banerjee, S. Shen, D.J. Kuck, and R.A. Towle. Time and parallel processor bounds for fortran-like loops. IEEE Transactions on Computers, C-28(9):660-670, September 1979.
	Ebc87	Kemal Ebcioğlu, A compilation technique for software pipelining of loops with conditional jumps, Proceedings of the 20th annual workshop on Microprogramming, p.69-79, December 01-04, 1987, Colorado Springs, Colorado, United States [doi>10.1145/255305.255317]
	EN90	K. Ebcioğlu , Toshio Nakatani, A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture, Selected papers of the second workshop on Languages and compilers for parallel computing, p.213-229, May 1990, Urbana, Illinois, United States
	Fis81	J.A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, C-30(7):478- 490, July t981.
	JA90	Reese B. Jones , Vicki H. Allan, Software pipelining: a comparison and improvement, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.46-56, November 27-29, 1990, Orlando, Florida, United States
	Jon91	R.B. Jones. Constrained Software Pipelining. Master's thesis, Utah State University, Logan, Utah, September 1991.
	Lam87	M.S. Lain. A Systolic Array Optimizing Compiler. PhD thesis, Carnegie Mellon University, 1987.
	Lam88	M. Lam, Software pipelining: an effective scheduling technique for VLIW machines, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.318-328, June 20-24, 1988, Atlanta, Georgia, United States
	NE89	T. Nakatani , K. Ebcioğlu, “Combining” as a compilation technique for VLIW architectures, Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture, p.43-55, August 14-16, 1989, Dublin, Ireland
	NP90	Alexandru Nicolau , Roni Potasman, Realistic scheduling: compaction for pipelined architectures, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.69-79, November 27-29, 1990, Orlando, Florida, United States
	SDX86	B. Su , S. Ding , J. Xia, URPR—An extension of URCR for software pipelining, Proceedings of the 19th annual workshop on Microprogramming, p.94-103, October 15-17, 1986, New York, New York, United States
	Smi87	Harry F. Smith, Data structures: form and function, Harcourt Brace & Co., Orlando, FL, 1987
	Veg82	Steven Roger Vegdahl, Local code generation and compaction in optimizing microcode compilers, 1982
	ZC91	Hans Zima , Barbara Chapman, Supercompilers for parallel and vector computers, ACM Press, New York, NY, 1990

CITED BY 10

	Nancy J. Warter-Perez , Noubar Partamian, Modulo scheduling with multiple initiation intervals, Proceedings of the 28th annual international symposium on Microarchitecture, p.111-119, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	Vivek Sarkar, Optimized unrolling of nested loops, Proceedings of the 14th international conference on Supercomputing, p.153-166, May 08-11, 2000, Santa Fe, New Mexico, United States
	Zhihong Tang , Gang Chen , Chihong Zhang , Yingwei Zhang , Bogong Su , Stanley Habib, GPMB—software pipelining branch-intensive loops, Proceedings of the 26th annual international symposium on Microarchitecture, p.21-30, December 01-03, 1993, Austin, Texas, United States
	Stephen R. Vegdahl, A dynamic-programming technique for compacting loops, ACM SIGMICRO Newsletter, v.23 n.1-2, p.180-188, Dec. 1992
	Nancy J. Warter , Grant E. Haab , Krishna Subramanian , John W. Bockhaus, Enhanced modulo scheduling for loops with conditional branches, ACM SIGMICRO Newsletter, v.23 n.1-2, p.170-179, Dec. 1992
	Michael Held , Manfred Glesner, Generating compilers for generated datapaths, Proceedings of the conference on European design automation, p.532-537, September 19-23, 1994, Grenoble, France
	Vivek Sarkar, Optimized Unrolling of Nested Loops, International Journal of Parallel Programming, v.29 n.5, p.545-581, October 2001
	Johannes Fürtler , Konrad J. Mayer , Werner Krattenthaler , Ivan Bajla, SPOT: development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing, Real-Time Imaging, v.9 n.6, p.387-399, December 2003
	Zhong Wang , Xiaobo Sharon Hu , Edwin H.-M. Sha, Register aware scheduling for distributed cache clustered architecture, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Sissades Tongsima , Chantana Chantrapornchai , Edwin H.-M. Sha , Nelson L. Passos, Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling, Journal of VLSI Signal Processing Systems, v.18 n.2, p.111-123, Feb. 1998