| Two-level adaptive training branch prediction |
| Full text |
Pdf
(1.13 MB)
|
| Source
|
International Symposium on Microarchitecture
archive
Proceedings of the 24th annual international symposium on Microarchitecture
table of contents
Albuquerque, New Mexico, Puerto Rico
Pages: 51 - 61
Year of Publication: 1991
ISBN:0-89791-460-0
|
|
Authors
|
|
Tse-Yu Yeh
|
Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
|
|
Yale N. Patt
|
Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 23, Downloads (12 Months): 177, Citation Count: 115
|
|
|
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
Michael Butler , Tse-Yu Yeh , Yale Patt , Mitch Alsup , Hunter Scales , Michael Shebanow, Single instruction stream parallelism is greater than two, Proceedings of the 18th annual international symposium on Computer architecture, p.276-286, May 27-30, 1991, Toronto, Ontario, Canada
|
 |
2
|
|
| |
3
|
Tse-Yu Yeh, "Two-Level Adaptive Training Branch Prediction", Technical Report, University of Michigan, (1991).
|
| |
4
|
Motorola inc., "M88100 User's Manual", Phoenix, Arizona, (March 13, 1989).
|
 |
5
|
|
 |
6
|
|
| |
7
|
|
| |
8
|
|
| |
9
|
|
 |
10
|
|
 |
11
|
|
 |
12
|
|
| |
13
|
J. Lee and A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design", IEEE Computer, (January 1984), pp.6-22.
|
 |
14
|
|
| |
15
|
|
| |
16
|
|
| |
17
|
L.E. Shar and E.S. Davidson, "A Multiminiprocessor System Implemented Through Pipelining.", IEEE Computer, (Feb. 1974), pp.42-51.
|
| |
18
|
T. C. Chen, "Parallelism, Pipelining and Computer Efficiency", Computer Design, Vol. 10, No. 1, (jan. 1971), pp.69-74.
|
CITED BY 115
|
|
|
|
|
Chih-Chieh Lee , I-Cheng K. Chen , Trevor N. Mudge, The bi-mode branch predictor, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.4-13, December 01-03, 1997, Research Triangle Park, North Carolina, United States
|
|
|
|
|
|
Nicolas Gloy , Michael D. Smith , Cliff Young, Performance issues in correlated branch prediction schemes, Proceedings of the 28th annual international symposium on Microarchitecture, p.3-14, November 29-December 01, 1995, Ann Arbor, Michigan, United States
|
|
|
|
|
|
Po-Ying Chang , Eric Hao , Yale N. Patt, Alternative implementations of hybrid branch predictors, Proceedings of the 28th annual international symposium on Microarchitecture, p.252-257, November 29-December 01, 1995, Ann Arbor, Michigan, United States
|
|
|
|
|
|
Quinn Jacobson , Eric Rotenberg , James E. Smith, Path-based next trace prediction, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.14-23, December 01-03, 1997, Research Triangle Park, North Carolina, United States
|
|
|
Eric Hao , Po-Yung Chang , Marius Evers , Yale N. Patt, Increasing the instruction fetch rate via block-structured instruction set architectures, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.191-200, December 02-04, 1996, Paris, France
|
|
|
Juan L. Aragón , José González , Antonio González , James E. Smith, Dual path instruction processing, Proceedings of the 16th international conference on Supercomputing, June 22-26, 2002, New York, New York, USA
|
|
|
|
|
|
Po-Yung Chang , Eric Hao , Tse-Yu Yeh , Yale Patt, Branch classification: a new mechanism for improving branch predictor performance, Proceedings of the 27th annual international symposium on Microarchitecture, p.22-31, November 30-December 02, 1994, San Jose, California, United States
|
|
|
Stuart Sechrest , Chih-Chieh Lee , Trevor Mudge, The role of adaptivity in two-level adaptive branch prediction, Proceedings of the 28th annual international symposium on Microarchitecture, p.264-269, November 29-December 01, 1995, Ann Arbor, Michigan, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Sanjay J. Patel , Tony Tung , Satarupa Bose , Matthew M. Crum, Increasing the size of atomic instruction blocks using control flow assertions, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.303-313, December 2000, Monterey, California, United States
|
|
|
|
|
|
Gary Tyson , Matthew Farrens , John Matthews , Andrew R. Pleszkun, A modified approach to data cache management, Proceedings of the 28th annual international symposium on Microarchitecture, p.93-103, November 29-December 01, 1995, Ann Arbor, Michigan, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Eric Hao , Po-Yung Chang , Yale N. Patt, The effect of speculatively updating branch history on branch prediction accuracy, revisited, Proceedings of the 27th annual international symposium on Microarchitecture, p.228-232, November 30-December 02, 1994, San Jose, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
David I. August , John W. Sias , Jean-Michel Puiatti , Scott A. Mahlke , Daniel A. Connors , Kevin M. Crozier , Wen-mei W. Hwu, The program decision logic approach to predicated execution, ACM SIGARCH Computer Architecture News, v.27 n.2, p.208-219, May 1999
|
|
|
|
|
|
Alan J. Drake , Todd D. Basso , Spencer M. Gold , Keith L. Kraver , Phiroze N. Parakh , Claude R. Gauthier , P. Sean Stetson , Richard B. Brown, CGaAs PowerPC FXU, Proceedings of the 37th conference on Design automation, p.730-735, June 05-09, 2000, Los Angeles, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
David I. August , Wen-mei W. Hwu , Scott A. Mahlke, A framework for balancing control flow and predication, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.92-103, December 01-03, 1997, Research Triangle Park, North Carolina, United States
|
|
|
|
|
|
Alexander V. Veidenbaum , Weiyu Tang , Rajesh Gupta , Alexandru Nicolau , Xiaomei Ji, Adapting cache line size to application behavior, Proceedings of the 13th international conference on Supercomputing, p.145-154, June 20-25, 1999, Rhodes, Greece
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
G. Palermo , M. Sam , C. Silvan , V. Zaccari , R. Zafalo, Branch prediction techniques for low-power VLIW processors, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
|
|
|
|
|
|
|
|
|
|
|
|
Colin Egan , Gordon Steven , Patrick Quick , Rubén Anguera , Fleur Steven , Lucian Vintan, Two-level branch prediction using neural networks, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.12-15, p.557-570, December 2003
|
|
|
Stephen Somogyi , Thomas F. Wenisch , Nikolaos Hardavellas , Jangwoo Kim , Anastassia Ailamaki , Babak Falsafi, Memory coherence activity prediction in commercial workloads, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.37-45, June 20-20, 2004, Munich, Germany
|
|
|
|
|
|
|
|
|
|
|
|
Scott A. Mahlke , Richard E. Hank , Roger A. Bringmann , John C. Gyllenhaal , David M. Gallagher , Wen-mei W. Hwu, Characterizing the impact of predicated execution on branch prediction, Proceedings of the 27th annual international symposium on Microarchitecture, p.217-227, November 30-December 02, 1994, San Jose, California, United States
|
|
|
Po-Yung Chang , Eric Hao , Yale N. Patt , Pohua P. Chang, Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution, Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, p.99-108, June 27-29, 1995, Limassol, Cyprus
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
M. Monchiero , G. Palermo , M. Sami , C. Silvano , V. Zaccaria , R. Zafalon, Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach, Integration, the VLSI Journal, v.38 n.3, p.515-524, January 2005
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Thomas M. Conte , Burzin A. Patel , J. Stan Cox, Using branch handling hardware to support profile-driven optimization, Proceedings of the 27th annual international symposium on Microarchitecture, p.12-21, November 30-December 02, 1994, San Jose, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Juan C. Moure , Domingo Benítez , Dolores I. Rexachs , Emilio Luque, Wide and efficient trace prediction using the local trace predictor, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A. Trias , J. Puiggalí , F. Castro , T. Jové , M. Sbert , J. L. Marzo, Speculative parallelization of multipath radiosity algorithm, Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems, p.89-95, July 13-16, 2009, Istanbul, Turkey
|
|