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Comparing static and dynamic code scheduling for multiple-instruction-issue processors
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Source International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents
Albuquerque, New Mexico, Puerto Rico
Pages: 25 - 33  
Year of Publication: 1991
ISBN:0-89791-460-0
Authors
Pohua P. Chang  Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
William Y. Chen  Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Scott A. Mahlke  Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Wen-mei W. Hwu  Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 12,   Citation Count: 6
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
Acosta 86
 
Amd
Advanced Micro Devices, 'Am29000 Streamlined Instruction Processor, Advance Information", Publication Number 09075, Rev. A, Amendment/0, Sunnyvale, California.
 
Chang 90
P. P. Chang, S. A. Mahlke, W. Y. Chen, and W. W. Hwu, "Code Optimization Techniques for Multiple-instructionissue Architectures," Center for Reliable and High-Performance Computing Report, Uiversity of Illinois, in preparation.
Cohn 89
Colwell 87
 
Ellis 86
 
Fisher 81
J.A Fisher, "Trace scheduling: A technique for global microcode compaction", iEEE Transactions on Uomputersj vol.c- 30, no.7, July 1981.
Fisher 83
 
Golumbic 90
Gross 86
Hennessy 83
Howland 87
Hwu 86
Hwu 89.3
 
Hwu 90
W.W. Hwu and Pohua P. Chang, 'Efficient Instruction Sequencing with Inline Target Insertion", Coordinated Science Laboratory Report, UILU-ENG-90- 2215, CSG-123, May, 1990.
 
IBM 90
IBM, Special Issue on IBM RISC System/6000 Processor, IBM Journal o/Research and Development, vol. 34, no. 1, January, 1990.
 
Intel 89
Intel, "i860(TM) 64-Bit Microprocessor", Order Number 240296-002, Santa Clara, California, April, 1989.
Jouppi 89
 
Kane 87
G. Kane, MIPS R~O00 RISC Architecture, Prentice Hall, Englewood Cliffs, NJ, 1987.
 
Kogge 81
P.M. Kogge, The Architecture of Pipelined Computers, pp.237-243, McGraw-Hill, 1981.
Lam 88
 
Nicolau 85
A. Nicolau, "Uniform parallelism exploitation in ordinary programs", Proceedings of the International Conference on Parallel Processing, pp.614-618, August, 1985.
Patt 85
Rau 81
 
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Smith 89
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Sohi 87
Sohi 89
 
Sparc 87
The SPARCTM Architecture Manual, Part No. 800-1399-07, Revision 50, SUN, Mountain View, California, August 1987.
 
Thornton 70
 
Tomasulo 67
R. M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal of Research and Development, vot.ll, pp.25-33, January, I967.
Uht 87
 
Warren 90
Weiss 87


Collaborative Colleagues:
Pohua P. Chang: colleagues
William Y. Chen: colleagues
Scott A. Mahlke: colleagues
Wen-mei W. Hwu: colleagues