| Comparing static and dynamic code scheduling for multiple-instruction-issue processors |
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International Symposium on Microarchitecture
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Proceedings of the 24th annual international symposium on Microarchitecture
table of contents
Albuquerque, New Mexico, Puerto Rico
Pages: 25 - 33
Year of Publication: 1991
ISBN:0-89791-460-0
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Authors
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Pohua P. Chang
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Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
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William Y. Chen
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Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
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Scott A. Mahlke
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Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
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Wen-mei W. Hwu
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Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
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Downloads (6 Weeks): 4, Downloads (12 Months): 12, Citation Count: 6
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 6
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William Y. Chen , Scott A. Mahlke , Wen-mei W. Hwu , Tokuzo Kiyohara , Pohua P. Chang, Tolerating data access latency with register preloading, Proceedings of the 6th international conference on Supercomputing, p.104-113, July 19-24, 1992, Washington, D. C., United States
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