Robust estimation of parametric yield under limited descriptions of uncertainty

ABSTRACT

Reliable prediction of parametric yield for a specific design is difficult; a significant reason is the reliance of the yield estimation methods on the hard-to-measure distributional properties of the process data. Existing methods are inadequate when dealing with real-life distributions of process and environmental parameters, and limited availability of parameter data during early design. This paper proposes a robust technique for full-chip parametric yield estimation; the proposed work is based on the rigorous notions of non-parametric robust statistics which permits estimation based on the knowledge of the range and the limited number of moments (e.g. mean and variance) of the parameter distributions. Fully or partially specified process and environmental parameters can be described by robust representations, and used to estimate probabilistic bounds for leakage dissipation. The proposed approach is applied to estimating the chip-level parametric yield. The experimental results show that the robust estimation algorithm improves the total leakage estimate by 5-13% at the 99^th percentile across distinct frequency bins, compared to using only the intervals of partially-specified parameters.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

General Terms:
Design, Performance