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Layer minimization of escape routing in area array packaging
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Source International Conference on Computer Aided Design archive
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
SESSION: Novel interconnect methodologies table of contents
Pages: 815 - 819  
Year of Publication: 2006
ISBN ~ ISSN:1092-3152 , 1-59593-389-1
Authors
Renshen Wang  University of California, San Diego La Jolla, CA
Rui Shi  University of California, San Diego La Jolla, CA
Chung-Kuan Cheng  University of California, San Diego La Jolla, CA
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 4,   Downloads (12 Months): 19,   Citation Count: 1
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ABSTRACT

We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. The triangular patterns are generated in a reverse order from the last to the first layer. We demonstrate that the triangular pin sequence maximizes the sum of escape pins in the accumulated layers and thus minimize the number of escape routing layers. A test case is presented to illustrate the approach.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
H. Bakoglu, "Circuits, Interconnections and Packaging in VLSI, Addison-Wesley, 1990.
 
2
E. Winkler, "Escape Routing from Chip Scale Packages," IEEE/CPMT Int. Electronics Manufacturing Technology Symp., pp. 393--401, 1996.
 
3
 
4
N. M. Gasparini, "A Method of Designing a Group of Bumps for C4 Packages to Maximize the Number of Bumps and Minimize the Number of Package Layers," Electronic Components and Technology Conference, pp. 695--696, 1994.
 
5
M. Horiuchi, E. Yoda, Y. Takeuchi, "Escape Routing Design to Reduce the Number of Layers in Area Array Packaging," IEEE Trans. on Advanced Packaging, vol.23, no.4, pp. 686--691, Nov. 2000.
 
6
 
7
R. Shi, H. Chen, C.-K. Cheng, D. Beckman, D. Huang, "Layer Count Reduction for Area Array Escape Routing," Int. Conf. & Exhibition on Device Packaging, Scottsdale, 2005


Collaborative Colleagues:
Renshen Wang: colleagues
Rui Shi: colleagues
Chung-Kuan Cheng: colleagues