Studying a GALS FPGA architecture using a parameterized automatic design flow

ABSTRACT

Routing delays dominate other delays in current FPGA designs. We have proposed a novel Globally Asynchronous Locally Synchronous (GALS) FPGA architecture called the GAPLA to deal with this problem. In the GAPLA architecture, The FPGA area is divided into locally synchronous blocks and the communications between them are through asynchronous I/O interfaces. An automatic design flow is developed for the GAPLA architecture. Starting from behavioral description, a design is partitioned into smaller modules and fit to GAPLA synchronous blocks. The asynchronous communications between modules are then sytthesized. The CAD flow is parameterized in modeling the GAPLA architecture. By manipulating the parameters, we could study different factors of the designed GAPLA arcitecturc. Our experimental results show an average of 20% performance improvement could be achieved by the GAPLA architecture.

REFERENCES

• 1: Jason Cong , Yiping Fan , Xun Yang , Zhiru Zhang, Architecture and synthesis for multi-cycle communication, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA [doi>10.1145/640000.640040]
• 2: William Tsu , Kip Macy , Atul Joshi , Randy Huang , Norman Walker , Tony Tung , Omid Rowhani , Varghese George , John Wawrzynek , André DeHon, HSRA: high-speed, hierarchical synchronous reconfigurable array, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.125-134, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296442]
• 3: Akshay Sharma , Katherine Compton , Carl Ebeling , Scott Hauck, Exploration of pipelined FPGA interconnect structures, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA [doi>10.1145/968280.968284]
• 4: Xin Jia, Ranga Vemuri. A novel asynchronous FPGA architecture design and its performanc evaluation. Proc. Int. Workshop Field Programmable Logic and Applications, 2005.
• 5: Xin Jia , Ranga Vemuri, CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture, Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design, p.251-256, January 03-07, 2006 [doi>10.1109/VLSID.2006.54]
• 6: Scott Hauck , Steven Burns , Gaetano Borriello , Carl Ebeling, An FPGA for Implementing Asynchronous Circuits, IEEE Design & Test, v.11 n.3, p.60-69, July 1994 [doi>10.1109/MDT.1994.303848]
• 7: Rob Payne, Self-Timed FPGA Systems, Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, p.21-35, September 01, 1995
• 8: Ryusuke Konishi , Hideyuki Ito , Hiroshi Nakada , Akira Nagoya , Norbert Imlig , Tsunemichi Shiozawa , Minoru Inamori , Kouichi Nagami , Kiyoshi Oguri, PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI, Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems, p.54, March 11-14, 2001
• 9: John Teifel , Rajit Manohar, Highly pipelined asynchronous FPGAs, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA [doi>10.1145/968280.968300]
• 10: Robert P. Dick , David L. Rhodes , Wayne Wolf, TGFF: task graphs for free, Proceedings of the 6th international workshop on Hardware/software codesign, p.97-101, March 15-18, 1998, Seattle, Washington, United States
• 11: Andrew Royal, Peter Cheung. Golbally asynchronous locally synchronous FPGA architectures. In Int. Workshop Field Programmable Logic and Applications 2003.
• 12: Alain Girault , Clément Ménier, Automatic Production of Globally Asynchronous Locally Synchronous Systems, Proceedings of the Second International Conference on Embedded Software, p.266-281, October 07-09, 2002
• 13: Song Peng, et al. Automated synthesis for asynchronous FPGAs. In Proc. FCCM, 2005.
• 14: D. Filo, D. C. Ku, X. Coelho, and G. Micheli. Interface optimization for concurrent systems under timing constraints. IEEE Trans. VLSI, 1(3), Sept. 1993.
• 15: David W. Hightower, A solution to line-routing problems on the continuous plane, Proceedings of the 6th annual conference on Design Automation, p.1-24, January 1969 [doi>10.1145/800260.809014]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design, Theory