Soft error reduction in combinational logic using gate resizing and flipflop selection

ABSTRACT

Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SER) of combinational logic circuits. First, we propose a gate sizing algorithm that trades off SER reduction and area overhead. This approach first computes bounds on the maximum achievable SER reduction by resizing a gate. This bound is then used to prune the circuit graph, arriving at a smaller set of candidate gates on which we perform incremental sensitivity computations to determine the gates that are the largest contributors to circuit SER. Second, we propose a flipflop selection method that uses slack information at each primary output node to determine the flipflop configuration that produces maximum SER savings. This approach uses an enhanced flipflop library that contains flipflops of varying temporal masking ability. Third, we propose a unified, cooptimization approach combining flipflop selection with the gate sizing algorithm. The joint optimization algorithm produces larger SER reductions while incurring smaller circuit overhead than either technique taken in isolation. Experimental results on a variety of benchmarks show SER reductions of 7.9X with gate sizing, 6.6X with flipflop assignment, and 28.2X for the combined optimization approach, with no delay penalties and area overheads within 5--6%. The runtimes for the optimization algorithms are on the order of 1--3 minutes.

REFERENCES

• 1: Robert Baumann, Soft Errors in Advanced Computer Systems, IEEE Design & Test, v.22 n.3, p.258-266, May 2005 [doi>10.1109/MDT.2005.69]
• 2: Premkishore Shivakumar , Michael Kistler , Stephen W. Keckler , Doug Burger , Lorenzo Alvisi, Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic, Proceedings of the 2002 International Conference on Dependable Systems and Networks, p.389-398, June 23-26, 2002
• 3: T. Karnik, B. Bloechel, K. Soumyanath, V. De, S. Borkar, "Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18μm," Symp. on VLSI Circuits, pp. 61--62, Jun 2001.
• 4: Subhasish Mitra , Norbert Seifert , Ming Zhang , Quan Shi , Kee Sup Kim, Robust System Design with Built-In Soft-Error Resilience, Computer, v.38 n.2, p.43-52, February 2005 [doi>10.1109/MC.2005.70]
• 5: T. Karnik, S. Vangal, S. Veeramachaneni, P. Hazucha, V. Erraguntla, S. Borkar, "Selective node engineering for chip-level soft error rate improvement," Symp. on VLSI Circuits, pp. 204--205, Jun 2002.
• 6: Subhasish Mitra , Tanay Karnik , Norbert Seifert , Ming Zhang, Logic soft errors in sub-65nm technologies design and CAD challenges, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065585]
• 7: M. Baze, S. Buechner, D. Mcmurrow, "A CMOS design technique for SEU hardening," IEEE Trans. on Nuclear Science (TNS), 47(6), pp. 263--2608, Dec 2000.
• 8: K. Moharam, N. Touba, "Cost-effective approach for reducing the soft error failure rate in logic circuits," Intl. Test Conf. (ITC), pp. 893--901, Sep 2003.
• 9: Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee, Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.288-293, March 07-11, 2005 [doi>10.1109/DATE.2005.274]
• 10: Quming Zhou , K. Mohanram, Cost-effective radiation hardening technique for combinational logic, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.100-106, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382551]
• 11: Yuvraj S. Dhillon , Abdulkadir U. Diril , Abhijit Chatterjee , Cecilia Metra, Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits, Proceedings of the 11th IEEE International On-Line Testing Symposium, p.35-40, July 06-08, 2005 [doi>10.1109/IOLTS.2005.41]
• 12: Chong Zhao , Sujit Dey, Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO), Proceedings of the 7th International Symposium on Quality Electronic Design, p.133-140, March 27-29, 2006 [doi>10.1109/ISQED.2006.75]
• 13: M. Zhang, N. Shanbhag, "An energy-efficient circuit technique for single event transient noise-tolerance," Intl. Symp. on Circuits and Systems (ISCAS), pp. 636--639, Jun 2005.
• 14: D. Mavis, P. Eaton, "Soft error rate mitigation techniques for modern microcircuits," Intl. Reliability Physics Symp. (IRPS), pp. 216--225, Apr 2002.
• 15: M. Zhang, N. Shanbhag, "A CMOS design style for logic circuit hardening," Intl. Reliability Physics Symp. (IRPS), pp. 223--229, Apr 2005.
• 16: Hungse Cha , Janak H. Patel, Latch Design for Transient Pulse Tolerance, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.385-388, October 10-12, 1994
• 17: Vivek Joshi , Rajeev R. Rao , David Blaauw , Dennis Sylvester, Logic SER Reduction through Flipflop Redesign, Proceedings of the 7th International Symposium on Quality Electronic Design, p.611-616, March 27-29, 2006 [doi>10.1109/ISQED.2006.82]
• 18: Praveen Elakkumanan , Kishan Prasad , Ramalingam Sridhar, Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic, Proceedings of the 7th International Symposium on Quality Electronic Design, p.617-624, March 27-29, 2006 [doi>10.1109/ISQED.2006.137]
• 19: J. Fishburn, A. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," Intl. Conf. on Computer-Aided Design (ICCAD), pp. 326--328, Nov 1985.
• 20: Chong Zhao , Xiaoliang Bai , Sujit Dey, A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996804]
• 21: Ming Zhang , N. R. Shanbhag, A soft error rate analysis (SERA) methodology, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.111-118, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382553]
• 22: R. Rajaraman , J. S. Kim , N. Vijaykrishnan , Y. Xie , M. J. Irwin, SEAT-LA: A Soft Error Analysis Tool for Combinational Logic, Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design, p.499-502, January 03-07, 2006 [doi>10.1109/VLSID.2006.143]
• 23: Rajeev R. Rao , Kaviraj Chopra , David Blaauw , Dennis Sylvester, An efficient static algorithm for computing the soft error rates of combinational circuits, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
• 24: Bin Zhang , Wei-Shen Wang , Michael Orshansky, FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs, Proceedings of the 7th International Symposium on Quality Electronic Design, p.755-760, March 27-29, 2006 [doi>10.1109/ISQED.2006.64]
• 25: L. B. Freeman, Critical charge calculations for a bipolar SRAM array, IBM Journal of Research and Development, v.40 n.1, p.119-129, Jan. 1996
• 26: P. Hazucha, C. Svensson, "Impact of CMOS technology scaling on atmospheric neutron soft error rate," IEEE Trans. on Nuclear Science (TNS), 47(6), pp. 2586--2594, Dec 2000.
• 27: F. Brglez, H. Fujiwara, "A neural netlist of ten combinational benchmark circuits and translator in Fortran," Intl. Symp. on Circuits and Systems (ISCAS), pp. 663--698, Jun 1985.
• 28: S. Yang, Logic synthesis and optimization benchmarks user guide, MCNC, Research Triangle Park, North Carolina, 1991.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic
      B.6.3 Design Aids
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
      B.7.2 Design Aids
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance, Verification