Soft error derating computation in sequential circuits

ABSTRACT

Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), the probability of system failure due to soft errors, is a key factor in design of cost-effective soft error resilient systems. We present a very fast and accurate approach based on enhanced static timing analysis and signal probabilities to estimate the probability of latching an incorrect value in the system bistables (timing derating). Experimental results and comparison with fault injections using timing accurate Monte-Carlo simulations show that the accuracy of our approach is within 1% while orders of magnitude faster.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.3 Reliability, Testing, and Fault-Tolerance**