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ABSTRACT
Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. Since NBTI is strongly dependent on the time for which the PMOS device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. This has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. Our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to NBTI. An analytical model for NBTI is derived using the framework of the Reaction-Diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. Simulations on ISCAS benchmarks under a 70nm technology show that NBTI causes a delay degradation of about 8% in combinational logic based circuits after 10 years (≈ 3 x 108s).
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. T. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, "NBTI Impact on Transistor and Circuit: Models, Mechanisms and Scaling Effects," in IEEE International Electronic Devices Meeting, pp. 14.5.1--14.5.4, December 2003.
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M. A. Alam, "On the Reliability of Micro-electronic Devices: An Introductory Lecture on Negative Bias Temperature Instability," in Nanotechnology 501 Lecture Series, September 2005. Available at http://www.nanohub.org/resources/?id=193.
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M. A. Alam, "A Critical Examination of the Mechanics of Dynamic NBTI for pMOSFETs," in IEEE International Electronic Devices Meeting, pp. 14.4.1--14.4.4, December 2003.
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M. A. Alam and S. Mahapatra, "A Comprehensive Model of PMOS NBTI Degradation," Journal of Microelectronics Reliability, vol. 45, pp. 71--81, August 2004.
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S. Mahapatra, P. B. Kumar, and M. A. Alam, "Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs," in IEEE Transactions on Electronic Devices, pp. 1371--1379, September 2004.
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B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, "Impact of NBTI on the Temporal Performance Degradation of Digital Circuits," IEEE Electron Device Letters, vol. 26, pp. 560--562, August 2003.
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S. Chakravarthi, A. T. Krishnan, V. Reddy, C. Machala, and S. Krishnan, "A Comprehensive Framework for Predictive Modeling of Negative Bias Temperature Instability," in Proceedings of the IEEE International Reliability Physics Symposium, pp. 273--282, April 2004.
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8
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G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, "Dynamic NBTI of p-MOS Transistors and its Impact on MOSFET Scaling," in IEEE Electron Device Letters, pp. 734--736, December 2002.
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Predictive Technology Model. Available at http://www.eas.asu.edu/ptm.
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W. Abadeer and W. Ellis, "Behavior of NBTI under AC Dynamic Circuit Conditions," in Proceedings of the IEEE International Reliability Physics Symposium, pp. 17--22, August 2003.
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CITED BY 14
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Wenping Wang , Shengqi Yang , Sarvesh Bhardwaj , Rakesh Vattikonda , Sarma Vrudhula , Frank Liu , Yu Cao, The impact of NBTI on the performance of combinational and sequential circuits, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
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Yu Wang , Hong Luo , Ku He , Rong Luo , Huazhong Yang , Yuan Xie, Temperature-aware NBTI modeling and the impact of input vector control on performance degradation, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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Kunhyuk Kang , Keejong Kim , Ahmad E. Islam , Muhammad A. Alam , Kaushik Roy, Characterization and estimation of circuit reliability degradation under NBTI using on-line IDDQ measurement, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
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