ACM Home Page
Please provide us with feedback. Feedback
Performance analysis of concurrent systems with early evaluation
Full text PdfPdf (225 KB)
Source International Conference on Computer Aided Design archive
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
SESSION: Thermal and variability issues in architectures table of contents
Pages: 448 - 455  
Year of Publication: 2006
ISBN ~ ISSN:1092-3152 , 1-59593-389-1
Authors
Jorge Júlvez  Universitat Politècnica de Catalunya, Barcelona, Spain
Jordi Cortadella  Universitat Politècnica de Catalunya, Barcelona, Spain
Michael Kishinevsky  SCL, Intel Corporation, Hillsboro
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 30,   Citation Count: 4
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1233501.1233590
What is a DOI?

ABSTRACT

Early evaluation allows to execute operations when enough information at the inputs has been received to determine the value at the outputs. Systems that can tolerate variable-latency units, such as latency-insensitive or asynchronous systems, can enhance their performance by using early evaluation. The most relevant example of a unit with early evaluation is the multiplexor: the output can be determined as soon as the information of the selected channel arrives, without waiting for the other channels.

This paper analyzes the potential impact of early evaluation in concurrent systems. An analytical model, based on a Petri net extension with early firing is proposed to estimate the performance. The reduction of the analytical model to a linear programming formulation for an efficient estimation of the upper bound for the system throughput is proposed. The results show the accuracy of the model and the benefits of early evaluation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Ajmone Marsan, G. Balbo, G. Conte, S. Donatelli, and G. Franceschinis. Modelling with Generalized Stochastic Petri Nets. Wiley, 1995.
 
2
C. Brej and J. Garside. Early output logic using anti-tokens. In Int. Workshop on Logic Synthesis, pages 302--309, May 2003.
 
3
 
4
L. Carloni, K. McMillan, and A. Sangiovanni-Vincentelli. Theory of latency-insensitive design. IEEE Transactions on Computer-Aided Design, 20(9):1059--1076, Sept. 2001.
 
5
F. Commoner, A. W. Holt, S. Even, and A. Pnueli. Marked directed graphs. Journal of Computer and System Sciences, 5:511--523, 1971.
 
6
A. Dasdan and R. K. Gupta. Faster maximum and minimum mean cycle algorithms for system performance analysis. IEEE Transactions on Computer-Aided Design, 17(10):889--899, 1998.
 
7
R. Karp. A characterization of the minimum cycle mean in a digraph. Discrete Mathematics, 23:309--311, 1978.
 
8
M. K. Molloy. Performance Analysis Using Stochastic Petri Nets. IEEE Trans. on Computers, 31(9):913--917, 1982.
 
9
T. Murata. Petri Nets: Properties, analysis and applications. Proceedings of the IEEE, pages 541--580, Apr. 1989.
 
10
R. Reese, M. Thornton, C. Traver, and D. Hemmendinger. Early evaluation for performance enhancement in phased logic. IEEE Transactions on Computer-Aided Design, 24(4):532--550, Apr. 2005.
 
11
J. Sparsø and S. Furber, editors. Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, 2001.
 
12


Collaborative Colleagues:
Jorge Júlvez: colleagues
Jordi Cortadella: colleagues
Michael Kishinevsky: colleagues