Decoupling capacitor planning and sizing for noise and leakage reduction

ABSTRACT

Decoupling capacitor (decap) is a popular means to reduce power supply noise in integrated circuits. Since the decaps are usually inserted in the whitespace of the device layer, decap management during the floorplanning stage is desirable. In this paper, we devise the Effective Decap Distance model to analyze how functional blocks are affected by non-neighboring decaps. In addition, we propose a generalized network flow-based algorithm to allocate the whitespace to the blocks and determine the oxide thicknesses for the decaps to be implemented in the whitespace. Experimental results show that our decap allocation and sizing methods can significantly reduce decap budget and leakage power with a small increase in area and wirelength when integrated into 2D and 3D floorplanners.

REFERENCES

• 1: S. Zhao, C. Koh, and K. Roy. Decoupling capacitance allocation and its application to power supply noise aware floorplanning. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 21(1):81--92, 2002.
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
3D floorplanning, decoupling capacitors, leakage power reduction, power supply noise