Voltage island aware floorplanning for power and timing optimization

ABSTRACT

Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction. The underlying idea behind MSV is the trade-off between power saving and performance. In this paper, we present an effective voltage assignment technique based on dynamic programming. Given a netlist without reconvergent fanouts, the dynamic programming can guarantee an optimal solution for the voltage assignment. We then generate a level shifter for each net that connects two blocks in different voltage domains, and perform power-network aware floorplanning for the MSV design. Experimental results show that our floorplanner is very effective in optimizing power consumption under timing constraints.

REFERENCES

• 1: Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337541]
• 2: Tung-Chieh Chen , Yao-Wen Chang, Modern floorplanning based on fast simulated annealing, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA [doi>10.1145/1055137.1055161]
• 3: K. Chaudhary and M. Pedram, "Computing the Area Versus Delay Trade-Off Curves in Technology Mapping," IEEE Trans. on Computer-Aided Design, vol. 14, Dec. 1995.
• 4: J. Chang , M. Pedram, Energy minimization using multiple supply voltages, Proceedings of the 1996 international symposium on Low power electronics and design, p.157-162, August 12-14, 1996, Monterey, California, United States
• 5: Jui-Ming Chang , Massoud Pedram, Energy minimization using multiple supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.436-443, Dec. 1997 [doi>10.1109/92.645070]
• 6: Meng-Chen Wu , Yao-Wen Chang, Placement with Alignment and Performance Constraints Using the B*-Tree Representation, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.568-571, October 11-13, 2004
• 7: Andrew B. Kahng, Classical floorplanning harmful?, Proceedings of the 2000 international symposium on Physical design, p.207-213, May 2000, San Diego, California, United States [doi>10.1145/332357.332401]
• 8: Kirkpatrick, Gelatt, and Vecchi, "Optimization by Simulated Annealing," Science, May 1983.
• 9: Sarvesh H. Kulkarni , Ashish N. Srivastava , Dennis Sylvester, A new algorithm for improved VDD assignment in low power dual VDD systems, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013287]
• 10: Ruchir Puri , Leon Stok , John Cohn , David Kung , David Pan , Dennis Sylvester , Ashish Srivastava , Sarvesh Kulkarni, Pushing ASIC performance in a power envelope, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.776032]
• 11: Kimiyoshi Usami , Mark Horowitz, Clustered voltage scaling technique for low-power design, Proceedings of the 1995 international symposium on Low power design, p.3-8, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224083]
• 12: K. Usami, M. Igarashi, F. Minami, M. Ishikawa, M. Ichida, and K. Nogami, "Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor," IEEE Trans. on Solid-State Circuits, pp.463--472, 1998.
• 13: Huaizhi Wu , I-Min Liu , M. D. F. Wong , Yusu Wang, Post-placement voltage island generation under performance requirement, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.309-316, November 06-10, 2005, San Jose, CA
• 14: Y.-J. Yeh and S.-Y. Kuo, "An Optimization-Based Low-Power Voltage Scaling Technique Using Multiple Supply Voltage," Proc. ISCAS, pp.535--538, 2001.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Routing and layout

  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
      I.2.8 Problem Solving, Control Methods, and Search
          Subjects: Dynamic programming

General Terms:
Algorithms, Design, Performance