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Analog placement with symmetry and other placement constraints
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Source International Conference on Computer Aided Design archive
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
SESSION: Analog design automation techniques table of contents
Pages: 349 - 354  
Year of Publication: 2006
ISBN ~ ISSN:1092-3152 , 1-59593-389-1
Authors
Yiu-Cheong Tam  The Chinese University of Hong Kong
Evangeline F. Y. Young  The Chinese University of Hong Kong
Chris Chu  Iowa State University
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 6,   Downloads (12 Months): 31,   Citation Count: 5
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ABSTRACT

In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously. The problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously. Instead of handling the constraints by having a penalty term in the cost function to penalize violations, a unified method is proposed that, by adjusting the edge weights in a pair of constraint graphs, can try to satisfy all the placement and symmetry constraints simultaneously in a candidate floorplan solution. The maximum distance of the modules in a symmetry group from the corresponding symmetry axis will be minimized in this weight adjusting step, in order to minimize the total packing area. We have compared our method with the most updated results on this problem [2] when there are only symmetry constraints and results show that our approach can give solutions of better quality, in an acceptable amount of run time. We will also demonstrate the effectiveness of our approach in handling different types of constraints simultaneously by testing on data sets with both symmetry and other placement constraints, and the results are very promising.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
F. Balasa and K. Lampaert. Symmetry within the Sequence-Pair Representation in the Context of Placement for Analog Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(7):712--731, 2000.
 
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F. Balasa, S. C. Maruvada, and K. Krishnamoorthy. On the Exploration of the Solution Space in Analog Placement with Symmetry Constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(2):177--191, 2004.
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J. Cohn, et al. KOAN/ANAGRAMII: New Tools for Device-Level Analog Layout. IEEE J. Solid-State Circuits, 26(3):330--342, 1991.
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K. Lampaert, G. Gielen, and W. Sansen. A Performance-driven Placement Tool for Analog Integrated Circuits. IEEE J. Solid-State Circuits, 30(7):773--780, 1995.
 
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J. M. Lin and Y. W. Chang. TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(6), 2004.
 
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E. Malavasi, E. Charbon, E. Felt, and A. Sangiovanni-Vincentelli. Automation of IC Layout with Analog Constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(8):923--942, 1996.
 
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Collaborative Colleagues:
Yiu-Cheong Tam: colleagues
Evangeline F. Y. Young: colleagues
Chris Chu: colleagues