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Application-specific customization of parameterized FPGA soft-core processors
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
SESSION: Power and performance optimizations on system level design table of contents
Pages: 261 - 268  
Year of Publication: 2006
ISBN ~ ISSN:1092-3152 , 1-59593-389-1
Authors
David Sheldon  University of California, Riverside
Rakesh Kumar  University of California, San Diego
Roman Lysecky  University of Arizona
Frank Vahid  University of California, Riverside
Dean Tullsen  University of California, San Diego
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are parameterized to support application-specific customization, wherein pre-defined units, such as a multiplication unit or floating-point unit, may be included in the microprocessor architecture to speed up software execution at the expense of increased size. We introduce a methodology for fast applicationspecific customization of a parameterized FPGA soft core, using synthesis and execution to obtain size and performance data in order to create a tool that can be used across a variety of tool platforms and FPGA devices. As synthesizing a soft core takes tens of minutes, developing heuristics that execute in an acceptable time of an hour or two, yet find near-optimal results, is a challenge. We consider two approaches, one using a traditional CAD approach that does an initial characterization using synthesis to create an abstract problem model and then explores the solution space using a knapsack algorithm, and the other using a synthesisin-the-loop exploration approach. We compare approaches for a variety of design constraints, on 11 EEMBC benchmarks, using an actual Xilinx soft-core processor, and for two different commercial Xilinx FPGA devices. Our results show that the approaches can generate a customized configuration exhibiting roughly 2x speedups over a base soft core, reaching within 4% of optimal in about 1.5 hours, including complete synthesis of the soft-core onto the FPGA, compared to over 11 hours for exhaustive search. Our results also show that including synthesisin-the-loop, compared to a traditional CAD approach, improved speedups by an average of 20% when size constraints were tight. The approaches may also be applicable to soft-core processors targeted to ASICs in addition to FPGAs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
David Sheldon: colleagues
Rakesh Kumar: colleagues
Roman Lysecky: colleagues
Frank Vahid: colleagues
Dean Tullsen: colleagues