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ABSTRACT
Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond 6 or 7 inputs because it enumerates all cuts and there are too many of them. We address the enumeration problem by introducing the notion of cut factorization. In cut factorization, one enumerates global and local cuts (collectively called the factor cuts) of the network, and uses these to generate other cuts. Depending on how global and local cuts are defined, one obtains different factorization schemes. In the first scheme, complete factorization, it is possible to generate any cut from factor cuts. However, complete factorization is expensive though less expensive than exhaustive enumeration. In the second scheme, partial factorization, there is no guarantee of generating all cuts from factor cuts. However, it is much faster, and produces good results. In this paper we also present two applications of factor cuts: LUT mapping and macrocell mapping. In LUT mapping, we find that considering only factor cuts guarantees depth optimality for most nodes in the network. For the remaining nodes, other cuts need to be generated from factor cuts and examined. In macrocell mapping, we focus on a particular 9-input macrocell, and use factor cuts as a heuristic method to improve depth by reducing structural bias. Factor cuts are used to map the macrocell as a whole whenever possible instead of mapping its parts separately. In this context factor cuts enable a new quality-run-time tradeoff between mapping parts of the macrocell separately (poor quality), and mapping using all 9-input cuts (long run-time).
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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Actel Corporation, "ProASIC3 Flash Family FPGAs Datasheet," Available from Actel website.
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2
|
Berkeley Logic Synthesis Group, The ABC Logic Synthesis System, UC Berkeley. http://www.eecs.berkeley.edu/~alanmi/abc/
|
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3
|
|
| |
4
|
S. Chatterjee , A. Mishchenko , R. Brayton , X. Wang , T. Kam, Reducing structural bias in technology mapping, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.519-526, November 06-10, 2005, San Jose, CA
|
| |
5
|
J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Trans. CAD, Vol.13, No. 1 (January 1994), pp. 1--12.
|
 |
6
|
Jason Cong , Chang Wu , Yuzheng Ding, Cut ranking and pruning: enabling a general and efficient FPGA mapping solution, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.29-35, February 21-23, 1999, Monterey, California, United States
[doi> 10.1145/296399.296425]
|
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7
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M. Hutton et al., "Improving FPGA Performance and Area using an Adaptive Logic Module," In Field Programming Logic and Application 2004, pp. 135--144.
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8
|
A. Ling, D. Singh and S. Brown, "FPGA Logic Synthesis using Quantified Boolean Satisfiability," In SAT '05, Springer LNCS Vol. 3569, pp. 444--450.
|
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9
|
|
 |
10
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|
 |
11
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CITED BY 4
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Yu Hu , Satyaki Das , Steve Trimberger , Lei He, Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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Andrew Kennings , Kristofer Vorwerk , Arun Kundu , Val Pevzner , Andy Fox, FPGA technology mapping with encoded libraries andstaged priority cuts, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA
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