| Exploring linear structures of critical path delay faults to reduce test efforts |
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International Conference on Computer Aided Design
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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San Jose, California
SESSION: Efficient delay test generation
table of contents
Pages: 100 - 106
Year of Publication: 2006
ISBN ~ ISSN:1092-3152 , 1-59593-389-1
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Downloads (6 Weeks): 9, Downloads (12 Months): 27, Citation Count: 0
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ABSTRACT
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target path can then be validated through simple calculation. Yet, no decomposition process is available to find paths that satisfy the above property. In this paper, given a set of target critical paths, we propose a two-stage method to find a set of robust-testable paths (with smaller number than the original set). The first stage constructs a necessary subset for critical robust paths, and the second stage identifies remaining functional sensitizable segments and their corresponding composing robust paths. The experiments show that a large percentage (several benchmarks close to 100%, 75% on average) of critical paths can be covered for most circuits. All paths and coverage are verified to match the best possible results. The data also indicate that the remaining hard-to-test (functional sensitizable) paths actually result from only a few tens of segments in the circuit (except for one circuit, s35932). DfT technique can then be applied to these uncovered segments for full testability with small overheads.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits. Boston, MA: Kluwer Academic Publishers, 1998.
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L.-C. Wang, J.-J. Liou, and K.-T. Cheng, "Critical Path Selection for Delay Fault Testing Based Upon a Statistical Timing Model," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 11, pp. 1550--1565, Nov. 2004.
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K. Fuchs, F. Fink, and M. H. Schulz, "Dynamite: An efficient automatic test pattern generation system for path delay faults," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, pp. 1323--1335, Oct. 1991.
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K. T. Cheng and H. C. Chen, "Classification and identification of nonrobust untestable path delay faults," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 845--853, Aug. 1996.
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U. Sparmann , D. Luxenburger , K.-T. Cheng , S. M. Reddy, Fast identification of robust dependent path delay faults, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.119-125, June 12-16, 1995, San Francisco, California, United States
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