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Exploring linear structures of critical path delay faults to reduce test efforts
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
SESSION: Efficient delay test generation table of contents
Pages: 100 - 106  
Year of Publication: 2006
ISBN ~ ISSN:1092-3152 , 1-59593-389-1
Authors
Shun-Yen Lu  National Tsing Hua University, Hsinchu, Taiwan
Pei-Ying Hsieh  National Tsing Hua University, Hsinchu, Taiwan
Jing-Jia Liou  National Tsing Hua University, Hsinchu, Taiwan
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target path can then be validated through simple calculation. Yet, no decomposition process is available to find paths that satisfy the above property. In this paper, given a set of target critical paths, we propose a two-stage method to find a set of robust-testable paths (with smaller number than the original set). The first stage constructs a necessary subset for critical robust paths, and the second stage identifies remaining functional sensitizable segments and their corresponding composing robust paths. The experiments show that a large percentage (several benchmarks close to 100%, 75% on average) of critical paths can be covered for most circuits. All paths and coverage are verified to match the best possible results. The data also indicate that the remaining hard-to-test (functional sensitizable) paths actually result from only a few tens of segments in the circuit (except for one circuit, s35932). DfT technique can then be applied to these uncovered segments for full testability with small overheads.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits. Boston, MA: Kluwer Academic Publishers, 1998.
 
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Collaborative Colleagues:
Shun-Yen Lu: colleagues
Pei-Ying Hsieh: colleagues
Jing-Jia Liou: colleagues