A delay fault model for at-speed fault simulation and test generation

ABSTRACT

We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. At-speed test application allows a circuit to be tested under its normal operation conditions. However, fault simulation and test generation for the existing fault models become significantly more complex due to the need to handle faulty signal-transitions that span multiple clock cycles. The proposed fault model alleviates this shortcoming by introducing unspecified values into the faulty circuit when fault effects may occur. Fault detection potentially occurs when an unspecified value reaches a primary output. Due to the uncertainty that an unspecified value propagated to a primary output will be different from the fault free value, an inherent requirement in this model is that a fault would be potentially detected multiple times in order to increase the likelihood of detection. Experimental results demonstrate that the model behaves as expected in terms of fault coverage and numbers of detections of target faults. A variation of an n-detection test generation procedure for stuck-at faults is used for generating test sequences under this model.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

General Terms:
Design, Performance, Verification