| From single core to multi-core: preparing for a new exponential |
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International Conference on Computer Aided Design
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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San Jose, California
SESSION: Embedded tutorial: from dual to multi to many core --- opportunities and challenges for supporting the new exponential
table of contents
Pages: 67 - 72
Year of Publication: 2006
ISBN ~ ISSN:1092-3152 , 1-59593-389-1
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Downloads (6 Weeks): 29, Downloads (12 Months): 151, Citation Count: 3
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ABSTRACT
In the past, processor design trends were dominated by increasingly complex feature sets, higher clock speeds, growing thermal envelopes and increasing power dissipation. Recently, clock speeds have tapered and thermal and power dissipation envelopes have remained flat. However, the demand for increasing performance continues which has fueled the move to integrated multiple processor (multi-core) designs. This paper discusses this trend towards multi-core processor designs, the design challenges that accompany it and a view of the research required to support it.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Gordon E. Moore, Cramming More Components onto Integrated Circuits. Electronics, April 19, 1965.
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Pham, D. et al. The Design and Implementation of a First-Generation CELL Processor. In ISSCC Digest of Technical Papers. (San Francisco, CA, USA, Feb 6-10, 2005) p. 184--5
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Jason Cong , Ashok Jagannathan , Glenn Reinman , Michail Romesis, Microarchitecture evaluation with physical planning, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
[doi> 10.1145/775832.775843]
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Ashok Jagannathan , Hannah Honghua Yang , Kris Konigsfeld , Dan Milliron , Mosur Mohan , Michail Romesis , Glenn Reinman , Jason Cong, Microarchitecture evaluation with floorplanning and interconnect pipelining, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
[doi> 10.1145/1120725.1120879]
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Jason Cong , Ashok Jagannathan , Yuchun Ma , Glenn Reinman , Jie Wei , Yan Zhang, An automated design flow for 3D microarchitecture evaluation, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
[doi> 10.1145/1118299.1118395]
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J. A. Darringer , R. A. Bergamaschi , S. Bhattacharya , D. Brand , A. Herkersdorf , J. K. Morrell , I. Nair , P. Sagmeister , Y. Shin, Early analysis tools for system-on-a-chip design, IBM Journal of Research and Development, v.46 n.6, p.691-707, November 2002
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Reinaldo A. Bergamaschi , Youngsoo Shin , Nagu Dhanwada , Subhrajit Bhattacharya , William E. Dougherty , Indira Nair , John Darringer , Sarala Paliwal, SEAS: a system for early analysis of SoCs, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
[doi> 10.1145/944645.944687]
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CITED BY 4
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Thang N. Bui , ThanhVu Nguyen , Joseph R. Rizzo, Jr., Parallel shared memory strategies for ant-based optimization algorithms, Proceedings of the 11th Annual conference on Genetic and evolutionary computation, July 08-12, 2009, Montreal, Québec, Canada
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