Analysis and modeling of CD variation for statistical static timing

ABSTRACT

Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused on the modeling of spatial correlation in SSTA. However, the vast majority of these works used artificially generated process data to test the proposed models. Hence, it is difficult to determine the actual effectiveness of these methods, the conditions under which they are necessary, and whether they lead to a significant increase in accuracy that warrants their increased runtime and complexity. In this paper, we study 5 different correlation models and their associated SSTA methods using 35420 critical dimension (CD) measurements that were extracted from 23 reticles on 5 wafers in a 130nm CMOS process. Based on the measured CD data, we analyze the correlation as a function of distance and generate 5 distinct correlation models, ranging from simple models which incorporate one or two variation components to more complex models that utilize principle component analysis and Quad-trees. We then study the accuracy of the different models and compare their SSTA results with the result of running STA directly on the extracted data. We also examine the trade-off between model accuracy and run time, as well as the impact of die size on model accuracy. We show that, especially for small dies (< 6.6mm x 5.7mm), the simple models provide comparable accuracy to that of the more complex ones, while incurring significantly less runtime and implementation difficulty. The results of this study demonstrate that correlation models for SSTA must be carefully tested on actual process data and must be used judiciously.

REFERENCES

• 1: Aseem Agarwal , David Blaauw , Vladimir Zolotov , Savithri Sundareswaran , Min Zhao , Kaushik Gala , Rajendran Panda, Statistical delay computation considering spatial correlations, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan [doi>10.1145/1119772.1119825]
• 2: M. Berkelaar, "Statistical Delay Calculation, a Linear Time Method," Proceedings of TAU97, Austin, TX, December 1997.
• 3: Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic, Fast statistical timing analysis by probabilistic event propagation, Proceedings of the 38th conference on Design automation, p.661-666, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379043]
• 4: Anirudh Devgan , Chandramouli Kashyap, Block-based Static Timing Analysis with Uncertainty, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.607, November 09-13, 2003 [doi>10.1109/ICCAD.2003.41]
• 5: H. Chang and S. S. Sapatnekar, "Statistical timing analysis under spatial correlations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 9 2005.
• 6: Hongliang Chang , Vladimir Zolotov , Sambasivan Narayan , Chandu Visweswariah, Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065604]
• 7: J. Cain and C. J. Spanos, "Electrical linewidth metrology for systematic CD variation characterization and causal analysis," Proceedings of SPIE Int. Soc. Opt. Eng. 2003.
• 8: S. B. Samaan, The impact of device parameter variations on the frequency and performance of VLSI chips, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.343-346, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382598]
• 9: C. E. Clark, "The greatest of a finite set of random variables," Operations Research, Volume 9, pp.85--91, 1961.
• 10: Paul Friedberg , Yu Cao , Jason Cain , Ruth Wang , Jan Rabaey , Costas Spanos, Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization, Proceedings of the 6th International Symposium on Quality of Electronic Design, p.516-521, March 21-23, 2005 [doi>10.1109/ISQED.2005.82]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Switching theory

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

General Terms:
Design, Performance