Practical variation-aware interconnect delay and slew analysis for statistical timing verification

ABSTRACT

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process and input signal variations are directly mapped into the variability of the output delay and slew. Since our approach produces delay and slew expressions parameterized in the underlying process variations, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.

REFERENCES

• 1: L. Pillage and R. Rohrer. Asymptotic waveform evaluation for timing analysis. IEEE Trans. Computer-Aided Design, 9:352--366, April 1990.
• 2: S. Nassif. Modeling and analysis of manufacturing variations. In Proc. IEEE Custom Integrated Circuits Conf., pages 223--228, 2001.
• 3: L. Daniel, O. Siong, L. Chay, K. Lee, and J. White. A multi-parameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models. IEEE Trans. Computer-Aided Design, 23(5):678--693, May 2004.
• 4: Peng Li , Frank Liu , Xin Li , Lawrence T. Pileggi , Sani R. Nassif, Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction, Proceedings of the conference on Design, Automation and Test in Europe, p.958-963, March 07-11, 2005 [doi>10.1109/DATE.2005.213]
• 5: Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani Nassif , Sarma Vrudhula, Variational delay metrics for interconnect timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996675]
• 6: J. Wang , P. Ghanta , S. Vrudhula, Stochastic analysis of interconnect performance in the presence of process variations, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.880-886, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382698]
• 7: C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]
• 8: C. Alpert, A. Devgan, and C. Kashyap. Rc delay metrics for performance optimization. IEEE Trans. Computer-Aided Design, 20:571--582, May 2001.
• 9: C. Kashyap, J. Alpert, F. Liu, and A. Devgan. Closed-form expressions for extending step delay and slew metrics to ramp inputs for rc trees. IEEE Trans. Computer-Aided Design, 23, April 2004.
• 10: C. Ratzlaff and L. Pillage. Rice: rapid interconnect circuit evaluation using awe. IEEE Trans. Computer-Aided Design, 13(6):763--776, June 1994.
• 11: Yaping Zhan , Andrzej J. Strojwas , Xin Li , Lawrence T. Pileggi , David Newmark , Mahesh Sharma, Correlation-aware statistical timing analysis with non-gaussian delay distributions, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065605]
• 12: H. B. Bakoglu. Circuits, interconnections and packaging for VLSI. Addison-Wesley, Reading, MA, 1990.
• 13: Kanak Agarwal , Dennis Sylvester , David Blaauw, Simple metrics for slew rate of RC circuits based on two circuit moments, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.776070]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Switching theory

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
      B.7.2 Design Aids
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance