| Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space |
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International Symposium on Physical Design
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Proceedings of the 2007 international symposium on Physical design
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Austin, Texas, USA
SESSION: Routing
table of contents
Pages: 151 - 158
Year of Publication: 2007
ISBN:978-1-59593-613-4
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Author
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Keith So
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University of New South Wales, Sydney, Australia
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Downloads (6 Weeks): 12, Downloads (12 Months): 44, Citation Count: 3
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ABSTRACT
The negotiated congestion mechanism forms the basis of most published FPGA routers today, with many routers projecting congestion and any other requirements onto a scalar search space to evaluate candidate paths. In this paper, we study the numerical stability of these scalar projections as the number of iterations increase. We show that in these scalar search spaces the norm of path costs increase exponentially with the number of iterations, leading to floating-point absorption and representation problems in computer arithmetic. We propose a novel two-component totally-ordered monoid space for path candidate evaluation, that guarantees the A* search finds a path with minimum congestion cost, and has linear norm growth with respect to the number of iterations. We demonstrate the efficacy of our new algorithm by testing on hard open routing problems in the FPGA Place and Route Challenge. The router successfully found 18 new routing solutions to instances that were previously unroutable, reducing the lowest track count to route 20 standard FPGA routing benchmarks by 10.2%.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Vaughn Betz. The "FPGA Place and Route Challenge". http://www.eecg.toronto.edu/~vaughn/challenge/challenge.html.
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[doi> 10.1145/611817.611828]
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Guy G. F. Lemieux , Stephen D. Brown , Daniel Vranesic, On two-step routing for FPGAS, Proceedings of the 1997 international symposium on Physical design, p.60-66, April 14-16, 1997, Napa Valley, California, United States
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Steven W. Oldridge and Steven J. E. Wilton. Placement and routing for FPGA architectures supporting wide shallow memories. In Proceedings of the 2003 IEEE International Conference on Field Programmable Technology, pages 154--161, 2003.
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