Early wire characterization for predictable network-on-chip global interconnects

ABSTRACT

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for upcoming nanometer technologies, where increased variations in both device characteristics and interconnect parameters introduce tedious design closure problems. The proposed methodology has been successfully applied to the wire synthesis of a Network-on-Chip interconnect to: (i) achieve a given delay and noise goals, and (ii) attain a more power-efficient design with respect to existing techniques.

REFERENCES

• 1: Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli, Coping with Latency in SOC Design, IEEE Micro, v.22 n.5, p.24-35, September 2002 [doi>10.1109/MM.2002.1044297]
• 2: Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond A. Kirkpatrick, The scaling challenge: can correct-by-construction design help?, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA [doi>10.1145/640000.640014]
• 3: S. Golson, ``Resistance is futile! building better wireload models,'' in Proc. of SNUG, 1999.
• 4: An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.206, October 12-15, 1997
• 5: P. Gopalakrishnan, et al., ``An analysis of the wire-load model uncertainty problem,'' in IEE Trans on CAD, 2002.
• 6: S. Bali, ``Does Single-Pass Physical Synthesis Work for FPGAs?'' in Journal of FPGA and Structured ASIC, 2004.
• 7: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 8: William J. Dally , Brian Towles, Route packets, not wires: on-chip inteconnection networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 9: M. Sgroi , M. Sheets , A. Mihal , K. Keutzer , S. Malik , J. Rabaey , A. Sangiovanni-Vencentelli, Addressing the system-on-a-chip interconnect woes through communication-based design, Proceedings of the 38th conference on Design automation, p.667-672, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379045]
• 10: Michael Gasteier , Manfred Glesner, Bus-based communication synthesis on system level, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.1-11, Jan. 1999 [doi>10.1145/298865.298866]
• 11: K. Lahiri et al., ``Design Space Exploration for Optimizing On-Chip Communication Architectures'', IEEE Trans on CAD, 2004.
• 12: Sudeep Pasricha , Nikil Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane, Floorplan-aware automated synthesis of bus-based communication architectures, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065727]
• 13: Jingcao Hu , Radu Marculescu, Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.10688, March 03-07, 2003
• 14: Srinivasan Murali , Luca Benini , Giovanni De Micheli, Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120737]
• 15: K. Srinivasan , K. S. Chatha , G. Konjevod, An automated technique for topology and route generation of application specific on-chip interconnection networks, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.231-237, November 06-10, 2005, San Jose, CA
• 16: Andreas Hansson , Kees Goossens , Andrei Rǎdulescu, A unified approach to constrained mapping and routing on network-on-chip architectures, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA [doi>10.1145/1084834.1084857]
• 17: S. Murali et al., "A Methodology for Mapping Multiple Use-Cases onto Networks on Chips ", Proc. of ASP-DAC, 2006.
• 18: Federico Angiolini , Paolo Meloni , Salvatore Carta , Luca Benini , Luigi Raffo, Contrasting a NoC and a traditional interconnect fabric with layout awareness, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
• 19: Terry Tao Ye , Giovanni De Micheli , Luca Benini, Analysis of power consumption on switch fabrics in network routers, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514051]
• 20: Hang-Sheng Wang , Xinping Zhu , Li-Shiuan Peh , Sharad Malik, Orion: a power-performance simulator for interconnection networks, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 21: Nilanjan Banerjee , Praveen Vellanki , Karam S. Chatha, A Power and Performance Model for Network-on-Chip Architectures, Proceedings of the conference on Design, automation and test in Europe, p.21250, February 16-20, 2004
• 22: G. Palemoro and C. Silvano, ``PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures'', in Proc. of PATMOS, 2004
• 23: Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
• 24: J. Cong, ``Challenges and Opportunities for Design Innovations in Nanometer Technologies,'' SRC Design Sciences Concept Paper, Tech. Rep., December 1997.
• 25: Cadence, Cadence SoC Encounter, www.cadence.com.
• 26: Synopsys, Synopsys PrimePower, www.synopsys.com.
• 27: B. Hendrickson, R. Leland, ``The Chaco User's Guide: Version 2.0'', Sandia Tech Report SAND94--2692, 1994. URL: //www.cs.sandia.gov~+bahendr/chaco.html

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance, Reliability

Keywords:
NoCs, design methodology, early wire characterization, global interconnects