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Symbolic simulation—techniques and applications
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents
Orlando, Florida, United States
Pages: 517 - 521  
Year of Publication: 1991
ISBN:0-89791-363-9
Author
Randal E. Bryant  School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 10,   Downloads (12 Months): 53,   Citation Count: 15
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ABSTRACT

Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. In one simulation run, a symbolic simulator can compute what would require many runs of a traditional simulator. Symbolic simulation has applications in both logic and timing verification, as well as sequential test generation. The concept of symbolic simulation has been discussed for over 10 years, but early attempts had only limited success. The recent introduction of more powerful, algorithmic methods of symbolic manipulation have had a major impact on the classes of circuits and properties that can be evaluated symbolically.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. G. Barrow. Proving the Correctness of Digital Hardware Designs. VLSI Design Vol. V, No. 7 (July 1984), 64-77.
 
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S. Bose and A. L. Fisher, "Verifying Pipelined Hardware Using Symbolic Logic Simulation," International Conference on Computer Design, October, 1989.
 
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J. L. Carter, et al, "Restricted Symbolic Evaluation is Fast and Useful," ICCAD-89, pp. 38-41.
 
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G. G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen, "ISAAC: A Symbolic Simulator for Analog Circuits," Journal of Solid-State Circuits, Vol. 24, No. 6 (December, 1989), pp. 1587-1597.
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C.4. Seger, and R. E. Bryant, "Modeling of Circuit Delays in Symbolic Simulation," IFIP Workshop on Applied Formal Methods for VLSI Design, November, 1989.
 
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E. Ulrich, and T. Baker, "The Concurrent Simulation of Nearly Identical Digital Networks", tEEE Computer (April, 1974), pp. 39--44.

CITED BY  15