| Symbolic simulation—techniques and applications |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 27th ACM/IEEE Design Automation Conference
table of contents
Orlando, Florida, United States
Pages: 517 - 521
Year of Publication: 1991
ISBN:0-89791-363-9
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Author
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Randal E. Bryant
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School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
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Downloads (6 Weeks): 9, Downloads (12 Months): 51, Citation Count: 15
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ABSTRACT
Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. In one simulation run, a symbolic simulator can compute what would require many runs of a traditional simulator. Symbolic simulation has applications in both logic and timing verification, as well as sequential test generation.
The concept of symbolic simulation has been discussed for over 10 years, but early attempts had only limited success. The recent introduction of more powerful, algorithmic methods of symbolic manipulation have had a major impact on the classes of circuits and properties that can be evaluated symbolically.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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H. G. Barrow. Proving the Correctness of Digital Hardware Designs. VLSI Design Vol. V, No. 7 (July 1984), 64-77.
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S. Bose and A. L. Fisher, "Verifying Pipelined Hardware Using Symbolic Logic Simulation," International Conference on Computer Design, October, 1989.
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R. E. Bryant , D. Beatty , K. Brace , K. Cho , T. Sheffler, COSMOS: a compiled simulator for MOS circuits, Proceedings of the 24th ACM/IEEE conference on Design automation, p.9-16, June 28-July 01, 1987, Miami Beach, Florida, United States
[doi> 10.1145/37888.37890]
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J. L. Carter, et al, "Restricted Symbolic Evaluation is Fast and Useful," ICCAD-89, pp. 38-41.
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William C. Carter , William H. Joyner, Jr. , Daniel Brand, Symbolic simulation for correct machine design, Proceedings of the 16th Conference on Design automation, p.280-286, June 25-27, 1979, San Diego, CA, United States
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G. G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen, "ISAAC: A Symbolic Simulator for Analog Circuits," Journal of Solid-State Circuits, Vol. 24, No. 6 (December, 1989), pp. 1587-1597.
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N. Ishiura , M. Takahashi , S. Yajima, Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits, Proceedings of the 26th ACM/IEEE conference on Design automation, p.497-502, June 25-28, 1989, Las Vegas, Nevada, United States
[doi> 10.1145/74382.74465]
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Nagisa Ishiura , Yutaka Deguchi , Shuzo Yajima, Coded time-symbolic simulation using shared binary decision diagram, Proceedings of the 27th ACM/IEEE conference on Design automation, p.130-135, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123240]
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C.4. Seger, and R. E. Bryant, "Modeling of Circuit Delays in Symbolic Simulation," IFIP Workshop on Applied Formal Methods for VLSI Design, November, 1989.
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E. Ulrich, and T. Baker, "The Concurrent Simulation of Nearly Identical Digital Networks", tEEE Computer (April, 1974), pp. 39--44.
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CITED BY 15
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L.-C. Wang , M. S. Abadir , J. Zeng, Measuring the effectiveness of various design validation approaches for PowerPCTM microprocessor arrays, Proceedings of the conference on Design, automation and test in Europe, p.273-277, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Li-C. Wang , Magdy S. Abadir , Nari Krishnamurthy, Automatic generation of assertions for formal verification of PowerPC microprocessor arrays using symbolic trajectory evaluation, Proceedings of the 35th annual conference on Design automation, p.534-537, June 15-19, 1998, San Francisco, California, United States
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Andreas Kuehlmann , Kenneth L. McMillan , Robert K. Brayton, Probabilistic state space search, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.574-579, November 07-11, 1999, San Jose, California, United States
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Manish Pandey , Richard Raimi , Derek L. Beatty , Randal E. Bryant, Formal verification of PowerPC arrays using symbolic trajectory evaluation, Proceedings of the 33rd annual conference on Design automation, p.649-654, June 03-07, 1996, Las Vegas, Nevada, United States
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Pei Hsin Ho , Thomas Shiple , Kevin Harer , James Kukula , Robert Damiano , Valeria Bertacco , Jerry Taylor , Jiang Long, Smart simulation using collaborative formal and simulation engines, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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Tamarah Arons , Elad Elster , Shlomit Ozer , Jonathan Shalev , Eli Singerman, Efficient symbolic simulation of low level software, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
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