| PHIGURE: a parallel hierarchical global router |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 27th ACM/IEEE Design Automation Conference
table of contents
Orlando, Florida, United States
Pages: 650 - 653
Year of Publication: 1991
ISBN:0-89791-363-9
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Authors
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Randall J. Brouwer
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Center for Reliable and High Performance Computing, University of Illinois at Urbana-Champaign, 1101 W. Springfield Ave., Urbana, IL
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Prithviraj Banerjee
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Center for Reliable and High Performance Computing, University of Illinois at Urbana-Champaign, 1101 W. Springfield Ave., Urbana, IL
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| Bibliometrics |
Downloads (6 Weeks): 12, Downloads (12 Months): 13, Citation Count: 2
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ABSTRACT
A new Parallel HIerarchical algorithm for Global Routing (PHIGURE) is presented in this paper. The router is based on the work of Burstein and Pelavin [1], but has many extensions for general global routing and parallel execution. Main features of the algorithm include structured hierarchical decomposition into separate independent tasks which are suitable for parallel execution and adaptive simplex solution for adding feedthroughs and adjusting channel heights for row-based layout. The algorithm is described and results are presented for a shared-memory multiprocessor implementation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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M. Burstoin and R, Pelavin, "Hierarchical Wire Routing," IEEE Trans. CAD, v ol. CAD-2, No. 4, pp. 223-234, Oct. 1983.
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P. Banerjee, "The Use of Parallel Processing in VLSI Computer-Aided Design Applications," ICCAD-88 Tutorial, also Tech. Report No. CSG-104, Coordinated Science Laboratory, Univ. of Illinois, Urbana, IL, May 1988.
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K.W. Lee and C. Sechen, "A New Global Router for Row-Based Layout," Proc. Int. Conf. Comt~uter-Aided Design, pp. 180-183, Nov. 1988.
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J. Cong and B. Preas, "A New Algorithm for Standard Cell Global Routing," Proc. Int. Conf. Computer-Aided Design, pp. 176-179, Nov. 1988.
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Y. Won and S. Sahni, "Maze Routing On A Hypercube Multiprocessor Computer," Proc. Int. Conf. on Parallel Processing, pp. 630-637, Aug. 1987.
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M. Marek-Sadowska, "Global Router for Gate Array," Proc. lnt. Conf. Computer Design, pp. 332-337, Oct. 1984.
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P.S. Tzeng and C. H. Sequin, "Codar: A Congestion- Directed General Area Router," Proc. Int. Conf. Computer-Aided Design, pp. 30-33, Nov. 1988.
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T. Watanabe, H. Kitazawa, and Y. Sugiyama, "A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor," IEEE Transactions Computer-Aided Design, vol. CAD-6, No 2, pp. 241-250, March 1987.
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