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ABSTRACT
We propose a general methodology to speed up the test generation process for circuits with high-level primitives. Our search procedure is a variation of depth first search that tries to fully exploit the capabilities of a computer to execute complex arithmetic and logical operations. We present techniques for signal value justification, and fault propagation, which are used by our algorithm. We have implemented a dependency-directed backtracking method to speed up our algorithm. This methodology has been applied to six circuits and the results are found to be very encouraging.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 10
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R. A. Bergamaschi , D. Brand , L. Stok , M. Berkelaar , S. Prakash, Efficient use of large don't cares in high-level and logic synthesis, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.272-278, November 05-09, 1995, San Jose, California, United States
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D. Crestani , A. Aguila , M.-H. Gentil , P. Chardon , C. Durante, Automatic partitioning for deterministic test, Proceedings of the conference on European design automation, p.322-325, November 1992, Congress Centrum Hamburg, Hamburg, Germany
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P. Vishakantaiah , J. Abraham , M. Abadir, Automatic test knowledge extraction from VHDL (ATKET), Proceedings of the 29th ACM/IEEE conference on Design automation, p.273-278, June 08-12, 1992, Anaheim, California, United States
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L. Stok , D. S. Kung , D. Brand , A. D. Drumm , L. N. Reddy , N. Hieter , D. J. Geiger , H. H. Chao , P. J. Osler , A. J. Sullivan, BooleDozer: logic synthesis for ASICs, IBM Journal of Research and Development, v.40 n.4, p.407-430, July 1996
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